1.4. Intel FPGA SerialLite III Streaming IP Core v17.1
|Added support for Intel® Stratix® 10 devices. New features include:
|No simplex receiver mode support for more than 17.4 Gbps data rate in Intel® Stratix® 10 devices.||Simplex receiver mode for greater than 17.4 Gbps data rate in Intel® Stratix® 10 is planned to be supported in future release.|
In previous versions of the Intel FPGA SerialLite III Streaming IP core design example] for Intel® Arria® 10 devices, the IOPLL and transceiver PLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs required additional constraints. This issue has been fixed in Intel® Quartus® Prime version 17.1.
If you are migrating earlier designs with these additional constraints to Intel® Quartus® Prime version 17.1, refer to the How to I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock? KDB link for more information.
|SerialLite III Streaming IP core in Intel® Stratix® 10 devices does not support Riviera™-Pro 2017.02 simulator.||You may use Riviera-Pro simulator prior to 2017.02 version.|
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