Serial Lite III Streaming Intel FPGA IP Core Release Notes

ID 683807
Date 12/19/2022
Public

1.2. Serial Lite III Streaming Intel FPGA IP Core v18.1

Table 2.  v18.1 September 2018
Description Impact
Added E-Tile transceiver support up to 28.0 Gbps data rate with x4 lane.
Note: The Serial Lite III Streaming IP with E-Tile transceiver supports only duplex core.
Added the following configuration and status registers:
  • TX Indirect Address
  • TX MAC Status
  • TX Lane#N MAC Status
  • TX Lane#N PCS Status
  • RX Indirect Address
  • RX MAC Status
  • RX Lane#N MAC Status
  • RX Lane#N PCS Status
Added the following bits in RX Error Status Register and RX Error Interrupt Enable Register:
  • Bit 11: RX Data Error
  • Bit 7: RX Adaptation FIFO Overflow
  • Bit 11: RX Data Error Interrupt Enable
  • Bit 7: RX Adaptation FIFO Overflow Interrupt Enable
Removed the following bits in RX Error Status Register and RX Error Interrupt Enable Register:
  • Bit 2: RX Loss of Frame Lock
  • Bit 2: RX Loss of Frame Lock Interrupt Enable
Riviera-PRO* simulator is not supported for Serial Lite III Streaming IP with E-Tile transceiver.
Added simulation, compilation, and hardware design example for Serial Lite III Streaming IP with E-Tile transceiver.

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