Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series

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ID 683780
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 F-Series and I-Series General-Purpose I/O Overview 2. Agilex™ 7 F-Series and I-Series GPIO Banks 3. Agilex™ 7 F-Series and I-Series HPS I/O Banks 4. Agilex™ 7 F-Series and I-Series SDM I/O Banks 5. Agilex™ 7 F-Series and I-Series I/O Troubleshooting Guidelines 6. Agilex™ 7 F-Series and I-Series General-Purpose I/O IPs 7. Programmable I/O Features Description 8. Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series User Guide Archives 9. Documentation Related to the Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series 10. Document Revision History for the Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series
1. Agilex™ 7 F-Series and I-Series General-Purpose I/O Overview x
1.1. Package Selection and I/O Vertical Migration Support 1.2. Types of I/O Banks
2. Agilex™ 7 F-Series and I-Series GPIO Banks x
2.1. GPIO Bank Overview 2.2. GPIO Features 2.3. GPIO Implementation Guide 2.4. GPIO Termination 2.5. GPIO Design Guidelines 2.6. GPIO Simulation
2.1. GPIO Bank Overview x
2.1.1. GPIO Bank Structure 2.1.2. GPIO Buffers and Registers
2.2. GPIO Features x
2.2.1. Supported I/O Standards for GPIO Banks 2.2.2. GPIO Buffer Behavior 2.2.3. Programmable I/O Element Features for the GPIO Bank
2.2.3. Programmable I/O Element Features for the GPIO Bank x
2.2.3.1. Guidelines: Programmable Output Slew Rate Control 2.2.3.2. Guidelines: Programmable Open-Drain Output 2.2.3.3. Guidelines: Programmable Bus-Hold 2.2.3.4. Guidelines: Programmable Pull-Up Resistor 2.2.3.5. Guidelines: Programmable De-Emphasis
2.3. GPIO Implementation Guide x
2.3.1. I/O Assignments with the Quartus® Prime Assignment Editor 2.3.2. Assigning Pin I/O Standards in the Quartus® Prime Pin Planner
2.3.1. I/O Assignments with the Quartus® Prime Assignment Editor x
2.3.1.1. Assigning Pin I/O Standards in the Quartus® Prime Assignment Editor 2.3.1.2. Assigning Programmable IOE Features in the Quartus® Prime Assignment Editor 2.3.1.3. GPIO Programmable IOE Features Assignment Names and Settings
2.4. GPIO Termination x
2.4.1. Single-Ended I/O Termination in F-Series and I-Series Devices 2.4.2. True Differential Signaling I/O Termination
2.4.1. Single-Ended I/O Termination in F-Series and I-Series Devices x
2.4.1.1. Single-Ended I/O Standards On-Chip Termination 2.4.1.2. OCT Calibration Block 2.4.1.3. Single-Ended I/O Standards External Termination 2.4.1.4. Single-Ended I/O Termination Implementation Guide
2.4.1.1. Single-Ended I/O Standards On-Chip Termination x
2.4.1.1.1. RS OCT 2.4.1.1.2. RT OCT 2.4.1.1.3. Dynamic OCT
2.4.1.4. Single-Ended I/O Termination Implementation Guide x
2.4.1.4.1. Configuring OCT Using the Assignment Editor 2.4.1.4.2. OCT Features Assignment Names and Settings
2.4.2. True Differential Signaling I/O Termination x
2.4.2.1. True Differential Signaling I/O Standard OCT Termination 2.4.2.2. True Differential Signaling I/O Standard External Termination
2.4.2.1. True Differential Signaling I/O Standard OCT Termination x
2.4.2.1.1. Configuring Differential Input RD OCT Using the Assignment Editor 2.4.2.1.2. Guidelines: Differential Input RD OCT
2.5. GPIO Design Guidelines x
2.5.1. VREF Sources and VREF Pins 2.5.2. I/O Standards Implementation Based on VCCIO_PIO Voltages 2.5.3. OCT Calibration Block Requirement 2.5.4. I/O Pins Placement Requirements 2.5.5. I/O Standard Selection and I/O Bank Supply Compatibility Check 2.5.6. Simultaneous Switching Noise 2.5.7. Special Pins Requirement 2.5.8. External Memory Interface Pin Placement Requirements 2.5.9. HPS Shared I/O Requirements 2.5.10. Clocking Requirements 2.5.11. SDM Shared I/O Requirements 2.5.12. Unused Pins 2.5.13. Voltage Setting for Unused GPIO Banks 2.5.14. GPIO Pins During Power Sequencing 2.5.15. Drive Strength Requirement for GPIO Input Pins 2.5.16. Maximum DC Current Restrictions 2.5.17. 1.2 V I/O Interface Voltage Level Compatibility 2.5.18. GPIO Pins for the Avalon® Streaming Interface Configuration Scheme 2.5.19. Maximum True Differential Signaling Receiver Pairs Per I/O Lane
2.6. GPIO Simulation x
2.6.1. IBIS Models—GPIO Support 2.6.2. HSPICE* Models 2.6.3. Net Length Reports
3. Agilex™ 7 F-Series and I-Series HPS I/O Banks x
3.1. HPS I/O Bank Overview 3.2. HPS I/O Features 3.3. HPS I/O Implementation Guide 3.4. HPS I/O Design Guidelines 3.5. HPS I/O Simulation
3.2. HPS I/O Features x
3.2.1. Supported I/O Standards for HPS I/O Banks 3.2.2. HPS I/O Buffer Behavior 3.2.3. Programmable I/O Element Features for the HPS I/O Bank
3.3. HPS I/O Implementation Guide x
3.3.1. Configuring Open Drain Feature for the HPS I/O 3.3.2. Configuring I/O Delays Feature for the HPS I/O 3.3.3. I/O Assignments with the Quartus® Prime Assignment Editor 3.3.4. Assigning Pin I/O Standards in the Quartus® Prime Pin Planner
3.3.3. I/O Assignments with the Quartus® Prime Assignment Editor x
3.3.3.1. Assigning Programmable IOE Features in the Quartus® Prime Assignment Editor 3.3.3.2. HPS I/O Programmable IOE Features Assignment Names and Settings
3.4. HPS I/O Design Guidelines x
3.4.1. Unused Pins 3.4.2. HPS I/O Pins During Power Sequencing 3.4.3. HPS Shared I/O Requirements
3.5. HPS I/O Simulation x
3.5.1. IBIS Models—HPS I/O Support 3.5.2. Net Length Reports
4. Agilex™ 7 F-Series and I-Series SDM I/O Banks x
4.1. SDM I/O Bank Overview 4.2. SDM I/O Features 4.3. SDM I/O Design Guidelines 4.4. SDM I/O Simulation
4.2. SDM I/O Features x
4.2.1. Supported I/O Standards for SDM I/O Banks 4.2.2. SDM I/O Buffer Behavior 4.2.3. I/O Standards and Features for Configuration Pins
4.3. SDM I/O Design Guidelines x
4.3.1. Unused Pins 4.3.2. SDM I/O Pins During Power Sequencing
4.4. SDM I/O Simulation x
4.4.1. IBIS Models—SDM I/O Support 4.4.2. Net Length Reports
6. Agilex™ 7 F-Series and I-Series General-Purpose I/O IPs x
6.1. GPIO Intel® FPGA IP 6.2. OCT Intel® FPGA IP
6.1. GPIO Intel® FPGA IP x
6.1.1. Release Information for GPIO Intel® FPGA IP 6.1.2. Generating the GPIO Intel® FPGA IP 6.1.3. GPIO Intel® FPGA IP Parameter Settings 6.1.4. GPIO Intel® FPGA IP Interface Signals 6.1.5. GPIO Intel® FPGA IP Architecture 6.1.6. Verifying Resource Utilization and Design Performance 6.1.7. GPIO Intel® FPGA IP Timing 6.1.8. GPIO Intel® FPGA IP Design Examples
6.1.2. Generating the GPIO Intel® FPGA IP x
6.1.2.1. Intel® FPGA IP Generation Output
6.1.3. GPIO Intel® FPGA IP Parameter Settings x
6.1.3.1. Guideline: Swap datain_h and datain_l Ports in Migrated IP
6.1.4. GPIO Intel® FPGA IP Interface Signals x
6.1.4.1. Shared Signals 6.1.4.2. Data Bit-Order for Data Interface 6.1.4.3. Input and Output Bus High and Low Bits 6.1.4.4. Data Interface Signals and Corresponding Clocks
6.1.5. GPIO Intel® FPGA IP Architecture x
6.1.5.1. GPIO Intel® FPGA IP Data Paths 6.1.5.2. Register Packing
6.1.5.1. GPIO Intel® FPGA IP Data Paths x
6.1.5.1.1. Input Path 6.1.5.1.2. Output and Output Enable Paths
6.1.7. GPIO Intel® FPGA IP Timing x
6.1.7.1. Timing Components 6.1.7.2. Delay Elements 6.1.7.3. Timing Analysis 6.1.7.4. Timing Closure Guidelines
6.1.7.3. Timing Analysis x
6.1.7.3.1. Single Data Rate Input Register 6.1.7.3.2. Full-Rate or Half-Rate DDIO Input Register 6.1.7.3.3. Single Data Rate Output Register 6.1.7.3.4. Full-Rate or Half-Rate DDIO Output Register
6.1.8. GPIO Intel® FPGA IP Design Examples x
6.1.8.1. GPIO Intel® FPGA IP Synthesizable Quartus® Prime Design Example 6.1.8.2. GPIO Intel® FPGA IP Simulation Design Example
6.2. OCT Intel® FPGA IP x
6.2.1. Release Information 6.2.2. Generating the OCT Intel® FPGA IP 6.2.3. OCT Intel® FPGA IP Parameter Settings 6.2.4. OCT Intel® FPGA IP Signals 6.2.5. QSF Assignments 6.2.6. OCT Intel® FPGA IP Architecture 6.2.7. OCT Intel® FPGA IP Design Example
6.2.2. Generating the OCT Intel® FPGA IP x
6.2.2.1. Intel® FPGA IP Generation Output
6.2.7. OCT Intel® FPGA IP Design Example x
6.2.7.1. Generating the Quartus® Prime Design Example
7. Programmable I/O Features Description x
7.1. Programmable Pre-Emphasis 7.2. Programmable De-Emphasis 7.3. Programmable Differential Output Voltage
1. Agilex™ 7 F-Series and I-Series General-Purpose I/O Overview
2. Agilex™ 7 F-Series and I-Series GPIO Banks
3. Agilex™ 7 F-Series and I-Series HPS I/O Banks
4. Agilex™ 7 F-Series and I-Series SDM I/O Banks
5. Agilex™ 7 F-Series and I-Series I/O Troubleshooting Guidelines
6. Agilex™ 7 F-Series and I-Series General-Purpose I/O IPs
7. Programmable I/O Features Description
8. Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series User Guide Archives
9. Documentation Related to the Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series
10. Document Revision History for the Agilex™ 7 General-Purpose I/O User Guide: F-Series and I-Series

6.1.7.2. Delay Elements

The Quartus® Prime software does not automatically set delay elements to maximize slack in the I/O timing analysis. To close the timing or maximize slack, set the delay elements manually in the Quartus® Prime settings file (.qsf).
Table 52.  Delay Elements .qsf AssignmentsSpecify these assignments in the .qsf to access the delay elements.
Delay Element .qsf Assignment
Input Delay Element set_instance_assignment –to <PIN> -name INPUT_DELAY_CHAIN <0..63>
Output Delay Element set_instance_assignment –to <PIN> -name OUTPUT_DELAY_CHAIN <0..15>
Output Enable Delay Element set_instance_assignment –to <PIN> -name OE_DELAY_CHAIN <0..15>

The Agilex™ M-series device datasheet provides information on delay chain specification and offset settings across fast and slow models. The Fast Model specifies the delay value when the maximum delay chain offset setting is selected using the fastest process. The Slow Model specifies the delay value when the maximum delay chain offset setting is selected using the slowest process within a specific speed grade.

For example, if you assign input delay chain setting to #10 using an Agilex™ M-series device with -1 speedgrade:

Minimum delay value = 10*Delay specification for Fast Model/63 = x ns

Maximum delay value = 10*Delay specification for -1V Slow Model/63 = y ns

The input delay ranges from x ns to y ns when -1 device speedgrade is selected in your design.

Note: The IOE delay chains are not process, voltage and temperature (PVT) compensated, which means the delay chain value changes across PVT.
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