Quick-Start for Intel® Quartus® Prime Pro Edition Software

ID 683769
Date 10/22/2018

Step 4: Close Timing on your Design

The Timing Analyzer determines the timing relationships that the design must meet to function correctly and according to the timing specifications.
To perform timing analysis of a compiled design:
  1. Click Tools > Timing Analyzer .
  2. In the Tasks window, double-click Update Timing Netlist.
    This action includes Creating Timing Netlist and Read SDC File.
Figure 4. Timing Report

By contrasting the timing results with the design requirements, you can determine whether the design needs further optimization, or you can continue with the next steps in the flow.

For more information, refer to The Timing Analyzer chapter in the Intel® Quartus® Prime Pro Edition Handbook Volume 3 .