Quick-Start for Intel® Quartus® Prime Pro Edition Software

ID 683769
Date 10/22/2018
Public

Step 2: Constrain your Design

After adding design files to the project, you assign design elements to I/O pins, and apply appropriate timing constraints to correctly optimize fitting and analyze timing for the design.

  1. Click Processing > Start > Start Analysis and Synthesis to Run Analysis and Synthesis in the project
  2. Click Assignments > Pin Planner.
    Figure 2. Pin Planner Window
  3. In the Pin Planner window, specify pin location, I/O standard, current settings, and slew rate.
  4. Create a timing constraints file by clicking File > New and then clicking Synopsys* Design Constraints File.
  5. Specify constraints for clock characteristics, timing exceptions, and external signal setup and hold times before running analysis.
In addition to device I/O pins and timing constraints, the Intel® Quartus® Prime Pro Edition software allows you to define placement and hierarchical constraints.
For more information, refer to the Intel® Quartus® Prime Pro Edition User Guide: Design Constraints.

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