Step 2: Constrain your Design
After adding design files to the project, you assign design elements to I/O pins, and apply appropriate timing constraints to correctly optimize fitting and analyze timing for the design.
- Click to Run Analysis and Synthesis in the project
.Figure 2. Pin Planner Window
- In the Pin Planner window, specify pin location, I/O standard, current settings, and slew rate.
- Create a timing constraints file by clicking Synopsys* Design Constraints File. and then clicking
- Specify constraints for clock characteristics, timing exceptions, and external signal setup and hold times before running analysis.
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