Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.1 Release Notes: Intel FPGA Programmable Acceleration Card N3000

ID 683749
Date 7/01/2021
Public

Supported Features

Table 1.  Features of the Intel Acceleration Stack v1.1 for Intel® FPGA PAC N3000
Feature Description
Configurations
  • 2x2x25 GbE
  • 4x25 GbE
  • 8x10 GbE
OPAE
  • FPGA enumeration
  • FME device access
  • AFU device access
  • FPGA memory-mapped I/O (MMIO) register access
  • Access Intel® MAX® 10 board management controller (BMC) over SPI bus
  • Voltage and power monitoring through OPAE commands
  • Memory test over DMA
  • Network loopback (NLB) test
  • Graceful shutdown support using the fpgad tool
  • SEU detection
  • Data Plane Development Kit (DPDK) support
Runtime and Development Installers Enables easy installation of the release package for Intel® FPGA PAC N3000
Security
  • Intel® MAX® 10 Root-of-Trust Implementation
  • Support for Intel® MAX® 10 BMC firmware, Intel® MAX® 10 FPGA images and FPGA static region user image signing
  • New OPAE security tools:
    • FPGA one-time secure update (fpgaotsu): Upgrades from unsecured MAX10 to a secured MAX10
    • FPGA secure update (fpgasupdate): Remotely updates bitstreams securely. fpgasupdate replaces fpgaflash.
    • Super-RSU (super-rsu): Supports v1.1 package updates ( Intel® MAX® 10 BMC firmware and FPGA image).
    • PACSign: Enables signing of bitstreams. To use this tool, you must have the capability to generate a public/private key pair and your hardware security module (HSM) must support a Public-Key Cryptography Standards (PKCS)#11 compatible application programming interface (API) to the PACSign tool.
Programmable Forward Error Correcting (FEC) Allows you to program the C827 Re-timers with Reed Solomon FEC (IEEE 802.3 Clause 108), Fire Code FEC (IEEE 802.3 Clause 74), or no-FEC for 25 GbE interfaces.

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