Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.1 Release Notes: Intel FPGA Programmable Acceleration Card N3000

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ID 683749
Date 7/01/2021
Public
Document Table of Contents
Document Table of Contents x
Notice Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.1 Release Notes Appendix: Intel Provided FPGA Factory Image Packet Drop
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.1 Release Notes x
Minimum Requirements Supported Features Intel Acceleration Stack v1.1 for Intel FPGA PAC N3000 Reference Table Known Issues Component Information Supported Software Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs v1.1 Release Notes
Component Information x
Broadcom* PEX8747 PCIe* Switch Intel Ethernet Controller XL710
Supported Software x
Data Plane Development Kit (DPDK) Intel® Network Adapter Drivers
Notice
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.1 Release Notes
Appendix: Intel Provided FPGA Factory Image Packet Drop

Intel Ethernet Controller XL710

Limitation Details
For packets below 160 bytes, there is a hardware packet processing limit for the entire device of ~37 Mpps. Refer to section Intel® Ethernet Controller X710/XXV710/XL710 Throughput Limit in document: Intel® Ethernet Controller X710/ XXV710/XL710 Specification Update.
The Intel XL710 Ethernet controller on the Intel® FPGA PAC N3000 does not support Wake-On-LAN. -
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