2.1. Tool Integration
DSP Builder for Intel® FPGAs is interoperable with other Simulink blocksets. In particular, you can use the basic Simulink blockset to create interactive testbenches. The automatic testbenches allows you to compare Simulink simulation results with the output of the ModelSim simulator that simulates the HDL generated for your DSP Builder design.
You can run the ModelSim simulator from within DSP Builder for Intel® FPGAs, if the ModelSim executable is in your path. You can use a script to integrate between the DSP Builder for Intel® FPGAs advanced blockset and the ModelSim simulator. The automatic testbench flow runs a test and returns a result indicating whether or not the outputs match.
Intel® Quartus® Prime
The advanced blockset allows you to build high-speed, high-performance DSP datapaths. In most production designs there is an RTL layer surrounding this datapath to perform interfacing to processors, high speed I/O, memories, and so on. To complete the design, use Platform Designer or RTL to assign board level components. Intel® Quartus® Prime can then complete the synthesis and place-and-route process. You can automatically load a design into Intel® Quartus® Prime by clicking on the Run Quartus Prime block in the top-level model.
DSP Builder for Intel® FPGAs creates a conduit interface and hw.tcl file for each advanced blockset design. It creates a memory-mapped interface only if the design contains interface blocks or external memory blocks. It can also create an Avalon® Streaming interface. The hw.tcl file can expose the processor bus for connection in Platform Designer. A DSP Builder for Intel® FPGAs advanced blockset subsystem is available from the System Contents tab in Platform Designer after you add the path to the hw.tcl file to the Platform Designer IP search path
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