Remote Update Intel® FPGA IP User Guide

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ID 683695
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Remote Update Intel® FPGA IP User Guide
1. Remote Update Intel® FPGA IP User Guide x
1.1. Release Information for Remote Update Intel® FPGA IP 1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP 1.3. Arria® 10 and Cyclone® 10 GX Devices 1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices 1.5. Cyclone IV and Intel Cyclone 10 LP Devices 1.6. Flash Memory Programming Files 1.7. Design Examples 1.8. Remote Update Intel® FPGA IP User Guide Archives 1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
1.3. Arria® 10 and Cyclone® 10 GX Devices x
1.3.1. Remote System Configuration Mode 1.3.2. Remote System Configuration Components 1.3.3. Parameter Settings 1.3.4. Ports 1.3.5. Parameters 1.3.6. Avalon® Memory-Mapped Interface 1.3.7. Enabling Remote System Upgrade Circuitry 1.3.8. Generating Initial RSU Image
1.3.1. Remote System Configuration Mode x
1.3.1.1. Remote System Upgrade State Machine
1.3.1.1. Remote System Upgrade State Machine x
1.3.1.1.1. Switching from Factory to Application Image or from Initial Application Image to Other Application Image
1.3.6. Avalon® Memory-Mapped Interface x
1.3.6.1. Control Status Register Signals 1.3.6.2. Register Map
1.3.6.1. Control Status Register Signals x
1.3.6.1.1. Control Status Register Write Operation 1.3.6.1.2. Control Status Register Read Operation 1.3.6.1.3. Operations Example Waveforms
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices x
1.4.1. Remote System Configuration Mode 1.4.2. Remote System Configuration Components 1.4.3. Parameter Settings 1.4.4. Ports 1.4.5. Parameters 1.4.6. Avalon® Memory-Mapped Interface 1.4.7. Enabling Remote System Upgrade Circuitry
1.4.6. Avalon® Memory-Mapped Interface x
1.4.6.1. Control Status Register Signals 1.4.6.2. Register Map
1.4.6.1. Control Status Register Signals x
1.4.6.1.1. Control Status Register Write Operation 1.4.6.1.2. Control Status Register Read Operation
1.5. Cyclone IV and Intel Cyclone 10 LP Devices x
1.5.1. Remote System Configuration Mode 1.5.2. Remote System Configuration Components 1.5.3. Parameter Settings 1.5.4. Ports 1.5.5. Parameters 1.5.6. Remote Update Operation 1.5.7. Avalon® Memory-Mapped Interface 1.5.8. Enabling Remote System Upgrade Circuitry
1.5.7. Avalon® Memory-Mapped Interface x
1.5.7.1. Control Status Register Signals 1.5.7.2. Register Map 1.5.7.3. Read Source Mapping
1.5.7.1. Control Status Register Signals x
1.5.7.1.1. Control Status Register Write Operation 1.5.7.1.2. Control Status Register Read Operation
1.7. Design Examples x
1.7.1. Intel Arria 10 Remote Update Design Example 1.7.2. Cyclone® V Remote Update Design Example
1. Remote Update Intel® FPGA IP User Guide

1.4.6.2. Register Map

Table 13.   Remote Update Intel® FPGA IP Avalon® Memory-Mapped Interface Register Map for Arria® V, Cyclone® V, Stratix® IV, and Stratix® V Devices
  • The IP core can read or write each field separately as each command has different parameter value.
  • The default value for the registers is 0.
Register Name Address Offset Width R/W Description
RU_RECONFIG_TRIGGER_CONDITIONS 0x0 5 Read Read configuration trigger conditions.
  • Bit 4—wdtimer_source: Users watchdog timer timeout
  • Bit 3—nconfig_source: External configuration reset (nCONFIG) assertion.
  • Bit 2—runconfig_source: Configuration reset triggered from logic array
  • Bit 1—nstatus_source: nSTATUS asserted by an external device as the result of an error
  • Bit 0—crcerror_source: CRC error during application configuration.
RU_WATCHDOG_TIMEOUT 0x1 12 Read/Write Read or write watchdog timeout value.
RU_WATCHDOG_ENABLE 0x2 1 Read/Write Enable or disable watchdog timeout.
  • 0: Disable
  • 1: Enable
RU_PAGE_SELECT 0x3 24 or 32 Read/Write Read or write start address of configuration image.
RU_CONFIGURATION_MODE 0x4 1 Read/Write Write configuration mode set to 1 in application page and 0 in factory page.
RU_RESET_TIMER 0x5 1 Write

Write a value of 1 to this register to trigger reset timer of the remote update. The IP will automatically trigger a reset pulse to reset timer pin of the remote update.

RU_RECONFIG 0x6 1 Write

Write a value of 1 to this register to trigger reconfiguration from a new image. The IP will set 1 to reconfig pin of the remote update and hold this value until the process done.

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