Visible to Intel only — GUID: sss1431432522908
Ixiasoft
1.1. Release Information for Remote Update Intel® FPGA IP
1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP
1.3. Arria® 10 and Cyclone® 10 GX Devices
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices
1.5. Cyclone IV and Intel Cyclone 10 LP Devices
1.6. Flash Memory Programming Files
1.7. Design Examples
1.8. Remote Update Intel® FPGA IP User Guide Archives
1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
Visible to Intel only — GUID: sss1431432522908
Ixiasoft
1.5.7.1.2. Control Status Register Read Operation
To execute the read operation for the control status register, perform the following steps:
- Asserts avl_csr_read signal high.
- Write a correct address of the register in the avl_csr_address bus. Refer to the Register Map for register information.
- Wait for the avl_csr_readdata_valid signal to go high.
- Retrieve read data from avl_csr_readdata.