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1.1. Release Information for Remote Update Intel® FPGA IP
1.2. Avalon® Memory-Mapped Interface in Remote Update Intel® FPGA IP
1.3. Arria® 10 and Cyclone® 10 GX Devices
1.4. Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices
1.5. Cyclone IV and Intel Cyclone 10 LP Devices
1.6. Flash Memory Programming Files
1.7. Design Examples
1.8. Remote Update Intel® FPGA IP User Guide Archives
1.9. Document Revision History for the Remote Update Intel® FPGA IP User Guide
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1.3.6.1. Control Status Register Signals
Name | Width | Direction | Description |
---|---|---|---|
clk | 1 | Input | Clock input. |
reset | 1 | Input | Reset input. |
avl_csr_address | 3 | Input | Address bus. |
avl_csr_read | 1 | Input | Perform a read transaction. |
avl_csr_write | 1 | Input | Perform a write transaction. |
avl_csr_readdata | 32 | Output | Read data from IP. |
avl_csr_readdata_valid | 1 | Output | Indicate when read data is valid. |
avl_csr_writedata | 32 | Input | Write data to IP. |
avl_csr_waitrequest | 1 | Output | Waitrequest signal high indicates the core is busy. |