1.4. Performance
Nios II Instruction Interface | Random Access | Sequential Access |
---|---|---|
Normal | 5 | 5 |
Flash Accelerator | 5 | 1 |
For a normal instruction master, fetching sequential addresses from the Max 10 On-Chip Flash IP is considered a random access because it does not take advantage of the burst read feature of the Flash IP by default. Enabling the optional burstcount signal at the Instruction Master does not improve the sequential access because the wrap burst of 8 from the instruction Master will be translated to equivalent incremental burst of 2 or 4 at the Flash IP. The most optimum setup is to ensure that both the master and slave have the same burst count size.
Max 10 Device | Cache Line Size (bits) |
---|---|
10M08 | 64 |
10M16 | 128 |
10M25 | 128 |
10M50 | 128 |

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