Nios II Flash Accelerator Using Max10

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ID 683684
Date 6/30/2015
Public
Document Table of Contents
Document Table of Contents x
1. Nios II Flash Accelerator Using Max10
1. Nios II Flash Accelerator Using Max10 x
1.1. Introduction 1.2. Feature Description 1.3. Parameter 1.4. Performance 1.5. Document Revision History
1.2. Feature Description x
1.2.1. Cache Operation Block 1.2.2. Pre-fetch Block 1.2.3. Address Generator Block 1.2.4. Cache (Registers) Block 1.2.5. Interfaces
1. Nios II Flash Accelerator Using Max10

1.3. Parameter

The table below lists the user parameters to allow the Flash Accelerator to be configured via the Nios II Qsys GUI under the “Cache and Memory Interfaces” tab. They are only available when the Nios core is configured to be Nios II/f.
Table 1.  Flash Accelerator Qsys Parameters
Parameter Usage Configurable Option
Line Size

Determines the width of each cache line in bits:

Burstcount size = Line Size (bits)/32
  • None
  • 64 bits
  • 128 bits
Cache Size Determines the number of cache lines for the cache data 2, 4
Level Two Title