Nios II Flash Accelerator Using Max10

ID 683684
Date 6/30/2015

1.2.5. Interfaces

It is a 32-bit read-only Avalon-MM master interface. It has support for wrapping burst where the burst starts from the critical word first. The burst size is configurable through the line size parameter where the burst count size equals to Line Size divided by 32-bits data.

Note: The Max 10 on-chip flash IP “Read burst mode” parameter needs to be configured to wrapping burst.