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1. Intel Agilex® 7 Configuration User Guide
2. Intel Agilex® 7 Configuration Details
3. Intel Agilex® 7 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Intel Agilex® 7 Configuration Features
7. Intel Agilex® 7 Debugging Guide
8. Intel Agilex® 7 Configuration User Guide Archives
9. Document Revision History for the Intel Agilex® 7 Configuration User Guide
2.1. Intel Agilex® 7 Configuration Timing Diagram
2.2. Configuration Flow Diagram
2.3. Device Response to Configuration and Reset Events
2.4. Additional Clock Requirements for HPS and Transceivers
2.5. Intel Agilex® 7 Configuration Pins
2.6. Configuration Clocks
2.7. Intel Agilex® 7 Configuration Time Estimation
2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP Core
3.1.7.4.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. PFL II IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. PFL II IP Recommended Design Constraints for using CFI Flash
3.1.7.4.4. PFL II IP Recommended Constraints for Other Input Pins
3.1.7.4.5. PFL II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Skew Tolerance Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Intel® Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.7. Debugging Guidelines for RSU Configuration
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Intel Agilex® 7 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. E-Tile Transceivers May Fail To Configure
7.8. Understanding and Troubleshooting Configuration Pin Behavior
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3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration
This section describes the procedures on how to use the Parallel Flash Loader II Intel® FPGA IP (PFL II) core.
To target a MAX® II, MAX® V, or Intel® MAX® 10 device requires the use of Intel® Quartus® Prime Standard Edition software whereas targeting a Intel Agilex® 7 requires Intel® Quartus® Prime Pro Edition software.
The process of creating the Avalon-ST single device configuration design targeting a MAX® II, MAX® V, or Intel® MAX® 10 device involves three steps.
- Generate the AVST design for the MAX® device with the default option address.
- Create the Intel Agilex® 7 .pof file in setting the appropriate option bits.
- Regenerate the Parallel Flash Loader II Intel® FPGA IP with the option bits used to generate the Intel Agilex® 7 .pof file and recompile the Intel® MAX® 10 design.
You can find an Intel® MAX® 10 system design example that implements theParallel Flash Loader II Intel® FPGA IP for AVST x32 configuration mode in the installer package of the Intel Agilex® 7 F-Series Transceiver-SoC Development Kit.
Figure 31. Process for Using the Parallel Flash Loader II Intel® FPGA IP CoreFigure shows the process for using the Parallel Flash Loader II Intel® FPGA IP core, using MAX® II as an example.
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