Intel Agilex® 7 Configuration User Guide

ID 683673
Date 8/14/2023

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3.3.4. Debugging Guidelines for the JTAG Configuration Scheme

The JTAG configuration scheme overrides all other configuration schemes. The SDM is always ready to accept configuration over JTAG unless a security feature disables the JTAG interface. JTAG is particularly useful in recovering a device that may be in an unrecoverable state reached when trying to configure using a corrupted image.

An nCONFIG falling edge terminates any JTAG access and the device reverts to the MSEL-specified boot source. nCONFIG must be stable during JTAG configuration. nSTATUS follows nCONFIG during JTAG configuration. Consequently, nSTATUS also must be stable.

Unlike other configuration schemes, nSTATUS does not assert if an error occurs during JTAG configuration. You must monitor the error messages that the Intel® Quartus® Prime Pro Edition Programmer generates for error reporting.

Note: For Intel Agilex® 7 devices that support HPS, when you choose to configure the FPGA fabric first, the JTAG chain has no mechanism to redeliver the HPS boot information following a cold reset. Consequently, you must reconfig the device with the .sof file or avoid cold resets to continue operation.

Debugging Suggestions

Here are some debugging tips for JTAG:

  • Verify that the JTAG pin connections are correct.
  • If JTAG configuration is failing, check that the FPGA has successfully powered up and exited POR. One strategy is to check the hand shaking behavior between nCONFIG and nSTATUS by driving nCONFIG low and ensuring that nSTATUS also goes low.
  • Verify that the nCONFIG pin does not change state during JTAG configuration.
  • Another way to determine whether the device has exited the POR state is to use the Intel® Quartus® Prime Programmer to detect the device. If the programmer can detect the Intel Agilex® 7 device, it has exited the POR state.
  • If you are using an Intel® FPGA Download Cable II, reduce the cable clock speed to 6 MHz.
  • If you have multiple devices in the JTAG chain, try to disconnect other devices from the JTAG chain to isolate the Intel Agilex® 7 device.
  • If you specify the OSC_CLK_1 as the clock source for configuration, ensure that OSC_CLK_1 is running at the frequency you specify in the Intel® Quartus® Prime software.

  • For designs including the High Bandwidth Memory (HBM2) IP or any IP using transceivers, you must provide a free running and stable reference clock to the device before device configuration begins. All transceiver power supplies must be at the required voltage before configuration begins.
  • When the MSEL setting on the PCB is not JTAG, if you use the JTAG interface for reconfiguration after an initial reconfiguration using AS or the Avalon® -ST interface, the .sof must be in the file format you specified in the Intel® Quartus® Prime project. For example, if you initially configure the MSEL pins for AS configuration and configure using the AS scheme, a subsequent JTAG reconfiguration using a .sof generated for Avalon® -ST fails.
  • Clearing the RSU_STATUS command after the JTAG reconfiguration depends on your Intel® Quartus® Prime software version. In earlier Intel® Quartus® Prime software versions, the RSU_STATUS is not cleared after the JTAG reconfiguration. Starting with the Intel® Quartus® Prime 20.3 version, the system clears the RSU_STATUS after the JTAG reconfiguration.
  • Ensure that during the power up, no external component drives the nSTATUS signal low.
  • If the JTAG configuration is failing when MSEL is set to AS configuration mode, erase the QSPI flash device by loading the .jic file in the Intel® Quartus® Prime Programmer without configuring the helper image, start erasing the QSPI flash device, and then power cycle the board before retrying the JTAG configuration.