1. Intel® Agilex™ Configuration User Guide 2. Intel® Agilex™ Configuration Details 3. Intel® Agilex™ Configuration Schemes 4. Including the Reset Release Intel® FPGA IP in Your Design 5. Remote System Update (RSU) 6. Intel® Agilex™ Configuration Features 7. Intel® Agilex™ Debugging Guide 8. Intel® Agilex™ Configuration User Guide Archives 9. Document Revision History for the Intel® Agilex™ Configuration User Guide
2.1. Intel® Agilex™ Configuration Timing Diagram 2.2. Configuration Flow Diagram 2.3. Device Response to Configuration and Reset Events 2.4. Additional Clock Requirements for HPS and Transceivers 2.5. Intel® Agilex™ Configuration Pins 2.6. Configuration Clocks 2.7. Intel® Agilex™ Configuration Time Estimation 2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types 3.1.2. Enabling Avalon-ST Device Configuration 3.1.3. The AVST_READY Signal 3.1.4. RBF Configuration File Format 3.1.5. Avalon-ST Single-Device Configuration 3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme 3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
220.127.116.11.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins 18.104.22.168.2. PFL II IP Recommended Design Constraints for Using QSPI Flash 22.214.171.124.3. PFL II IP Recommended Design Constraints for using CFI Flash 126.96.36.199.4. PFL II IP Recommended Constraints for Other Input Pins 188.8.131.52.5. PFL II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types 3.2.2. AS Single-Device Configuration 3.2.3. AS Using Multiple Serial Flash Devices 3.2.4. AS Configuration Timing Parameters 3.2.5. Skew Tolerance Guidelines 3.2.6. Programming Serial Flash Devices 3.2.7. Serial Flash Memory Layout 3.2.8. AS_CLK 3.2.9. Active Serial Configuration Software Settings 3.2.10. Intel® Quartus® Prime Programming Steps 3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description 5.2. Guidelines for Performing Remote System Update Functions for Non-HPS 5.3. Commands and Responses 5.4. Quad SPI Flash Layout 5.5. Generating Remote System Update Image Files Using the Programming File Generator 5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image 5.6.3. Programming Flash Memory with the Initial Remote System Update Image 5.6.4. Reconfiguring the Device with an Application or Factory Image 5.6.5. Adding an Application Image 5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist 7.2. Intel® Agilex™ Configuration Architecture Overview 7.3. Understanding Configuration Status Using quartus_pgm command 7.4. Configuration File Format Differences 7.5. Understanding SEUs 7.6. Reading the Unique 64-Bit CHIP ID 7.7. E-Tile Transceivers May Fail To Configure 7.8. Understanding and Troubleshooting Configuration Pin Behavior
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
- 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.1.6. Updates with the Factory Update Image
In rare instances you may need to update flash memory with a new factory image and the associated decision firmware and decision firmware data.
An update may be required for the following reasons:
- If there are vulnerabilities in the firmware
- If there are errors in the firmware or in the factory image
Intel provides a safe solution for you to update the factory image and the associated decision firmware and decision firmware data remotely. The update process stores multiple copies of critical data so that if power is lost or the update is disrupted, the device is still able to restart and continue the update. The update continues automatically when power is restored. Here are the steps to perform the update:
- Generate the factory update image using the Programming File Generator. The image contains the new factory Image, decision firmware, and decision firmware data.
- Program the factory update image, (*.rpd) to an empty partition slot starting from a new sector boundary in the flash device.
- Trigger reconfiguration to load the update image from the starting address using one of the following methods:
- Trigger reconfiguration using the RSU_IMAGE_UPDATE command. This method does not require you to update CPB0 and CPB1.
- Trigger reconfiguration by pulsing the nCONFIG signal or power cycling the device. This method requires you to write the factory update image start address in both CPB0 and CPB1. After factory image updates, the SDM automatically removes the address from CPB0 and CPB1.
- The updated image performs the following operations:
- Erases and replaces the previous decision firmware and decision firmware data in the flash device.
- Reprograms the new factory image in the flash device.
- After the update completes, the update image removes itself from the flash and its address pointer from the CPB, then the SDM loads the updated decision firmware followed by the application image or the factory image if an application image is not available.
- If the update process used an application slot, you must restore the application image by writing the application image .rpd to the application slot and the CPB.
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