- 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5. Remote System Update (RSU)
Intel® Agilex™ devices support RSU feature to allow you to update the FPGA image and reconfigure the device remotely. RSU has the following advantages:
- Provides a mechanism to deliver feature enhancements and bug fixes without recalling your products
- Reduces time-to-market
- Extends product life
Using RSU and the Mailbox Client Intel® FPGA IP you can write configuration bitstreams to the AS x4 flash device. Then you can use the Mailbox Client Intel® FPGA IP to instruct the SDM to reconfigure the FPGA from the updated image. You can store multiple application images and a single factory image in the configuration device. Your design manages remote updates of the application images in the configuration device.
You can initiate reconfiguration by sending an SDM command to the Mailbox Client Intel® FPGA IP in your logic design. The RSU performs configuration error detection during and after the reconfiguration process. If errors in the application image occur, the SDM firmware loads the next application image, or revert to factory image if next application image is not available and provides error status information.
This chapter explains the remote system update implementation for active configuration schemes. The FPGA drives the RSU. For the Intel® Agilex™ SoC devices, HPS can drive the RSU process.
For passive configuration schemes, an external host implements remote system update rather than the Intel® Agilex™ device. The external host manages the configuration image and initiate FPGA reconfiguration with the new image as needed.
The following figure shows functional diagrams for typical remote system update processes.
Remote System Update Functional Description
Guidelines for Performing Remote System Update Functions for Non-HPS
Commands and Responses
Quad SPI Flash Layout
Generating Remote System Update Image Files Using the Programming File Generator
Remote System Update from FPGA Core Example
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