1. Intel® Agilex™ Configuration User Guide 2. Intel® Agilex™ Configuration Details 3. Intel® Agilex™ Configuration Schemes 4. Including the Reset Release Intel® FPGA IP in Your Design 5. Remote System Update (RSU) 6. Intel® Agilex™ Configuration Features 7. Intel® Agilex™ Debugging Guide 8. Intel® Agilex™ Configuration User Guide Archives 9. Document Revision History for the Intel® Agilex™ Configuration User Guide
2.1. Intel® Agilex™ Configuration Timing Diagram 2.2. Configuration Flow Diagram 2.3. Device Response to Configuration and Reset Events 2.4. Additional Clock Requirements for HPS and Transceivers 2.5. Intel® Agilex™ Configuration Pins 2.6. Configuration Clocks 2.7. Intel® Agilex™ Configuration Time Estimation 2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types 3.1.2. Enabling Avalon-ST Device Configuration 3.1.3. The AVST_READY Signal 3.1.4. RBF Configuration File Format 3.1.5. Avalon-ST Single-Device Configuration 3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme 3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
22.214.171.124.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins 126.96.36.199.2. PFL II IP Recommended Design Constraints for Using QSPI Flash 188.8.131.52.3. PFL II IP Recommended Design Constraints for using CFI Flash 184.108.40.206.4. PFL II IP Recommended Constraints for Other Input Pins 220.127.116.11.5. PFL II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types 3.2.2. AS Single-Device Configuration 3.2.3. AS Using Multiple Serial Flash Devices 3.2.4. AS Configuration Timing Parameters 3.2.5. Skew Tolerance Guidelines 3.2.6. Programming Serial Flash Devices 3.2.7. Serial Flash Memory Layout 3.2.8. AS_CLK 3.2.9. Active Serial Configuration Software Settings 3.2.10. Intel® Quartus® Prime Programming Steps 3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description 5.2. Guidelines for Performing Remote System Update Functions for Non-HPS 5.3. Commands and Responses 5.4. Quad SPI Flash Layout 5.5. Generating Remote System Update Image Files Using the Programming File Generator 5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image 5.6.3. Programming Flash Memory with the Initial Remote System Update Image 5.6.4. Reconfiguring the Device with an Application or Factory Image 5.6.5. Adding an Application Image 5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist 7.2. Intel® Agilex™ Configuration Architecture Overview 7.3. Understanding Configuration Status Using quartus_pgm command 7.4. Configuration File Format Differences 7.5. Understanding SEUs 7.6. Reading the Unique 64-Bit CHIP ID 7.7. E-Tile Transceivers May Fail To Configure 7.8. Understanding and Troubleshooting Configuration Pin Behavior
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
- 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.1.1. RSU Glossary
|Firmware||Firmware that runs on SDM. Implements many functions including the functions listed here:
|Decision firmware||Firmware to identify and load the highest priority image. Previous versions of this user guide refer to decision firmware as static firmware. Starting in version 19.1 of the Intel® Quartus® Prime software, you can use RSU to update this firmware.|
|Decision firmware data||Decision firmware data structure containing the following information:
|Configuration pointer block (CPB)||A list of application image addresses in order of priority. When you add an image address to this block, that image becomes the highest priority.|
|Sub-partition table (SPT)||Data structure to facilitate the management of the flash storage.|
|Application image||Configuration bitstream that implements your design. This image includes the SDM firmware.|
The backup application image that the RSU loads when all attempts to load an application image fail.
The factory image should provide enough functionality for the device to recover when all application images are corrupt. Once the factory image loads, you can program new application images to replace the failing images.
The SDM loads the factory image in the following circumstances:
The configuration system treats the factory image in the same way as it does an application image.
|Initial RSU image||Contains the factory image, the application images, the decision firmware, and the associated RSU data structures.|
|Factory update image||An image that updates the following RSU-related items in flash:
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