3.2.11. Debugging Guidelines for the AS Configuration Scheme
The AS configuration scheme operation is like earlier device families. However, there is one significant difference. Intel® Agilex™ devices using AS mode, try to load a firmware section from addresses 0, 512k, 1024k and 1536k in the serial flash device connected to the CS0 pin.
If the configuration bitstream does not include a valid image, the SDM asserts an error by driving nSTATUS low. You can recover from the error by reconfiguring the FPGA over JTAG, or by driving nCONFIG low.
SDM tristates AS pins, AS_CLK, AS_nRST, AS_DATA0-AS_DATA3, and AS_nCSO0-AS_nCSO3, only when the device powers on if you set MSEL to JTAG. If MSEL is either AS fast or normal, the SDM drives the AS pins until you power cycle the Intel® Agilex™ device. Unlike earlier device families, the AS pins are not tristated when the device enters user mode.
The AS configuration scheme has power-on requirements. If you use AS Fast mode, you must ramp all power supplies to the recommended operating condition within 10 ms. This ramp-up requirement ensures that the AS x4 device is within its operating voltage range when the Intel® Agilex™ device begins accessing the AS x4 device.
When using AS fast mode, all power supplies to the Intel® Agilex™ device must be fully ramped-up to the recommended operating conditions before the SDM releases from reset. To meet the PCIe* 100 ms power-up-to-active time requirement for CvP, all the power supplies to the Intel® Agilex™ device must be at the recommended operating range within 10 ms.
Here are some debugging tips for the AS configuration scheme:
- Ensure that the design meets the power-supply ramp requirements for fast AS mode. If using fast mode, all power supplies must ramp to the recommended operating condition within 10 ms.
- Ensure that the flash is powered up and ready to be accessed when the Intel® Agilex™ device exits power-on reset.
- If you are using an external clock source for configuration, ensure the OSC_CLK_1 pin is fed correctly, and the frequency matches the frequency you set for the OSC_CLK_1 in your Intel® Quartus® Prime Pro Edition project.
- Ensure the MSEL pins reflect the correct AS configuration scheme.
- If the AS configuration is failing due to a corrupt image inside the serial flash device and reprogramming does not resolve the problem, you have two possible solutions depending on the components you are using for configuration:
- If you are using a third-party programmer to configure the flash directly from an AS or JTAG header as shown in AS Programming Using Intel Quartus Prime or Third-Party Programmer change the MSEL setting to JTAG. Setting MSEL to JTAG prevents the corrupt image from loading automatically at power-on. Then, update the image in quad serial flash through the AS or JTAG header.
- If you are programming the flash device using the JTAG header as shown in Programming Your Serial Configuration Device Using JTAG, force the nCONFIG signal to low. When nCONFIG is low, the image cannot load from the quad SPI flash device. Then, update the image in quad serial flash through the JTAG header.
- If you are using AS x4 flash memories with AS Fast mode, you must ramp up all power supplies to the recommended operating condition within 10 ms. This ramp-up requirement ensures that the AS x4 device is within its operating voltage range when the Intel® Agilex™ device begins to access it.
- Check endianness of the .rpd if using a third-party programmer to program Quad SPI device. You should generate the .rpd as big endian.
- If you are using the OSC_CLK_1 clock source for configuration, ensure OSC_CLK_1 is free running and stable before SDM starts to load a bitstream from the Quad SPI device. The SDM starts configuration after the device exits the POR state if nCONFIG is held high.
- Try a lower AS clock frequency setting.
- If you drive nCONFIG signal using the external host, ensure it remains high during the AS x4 configuration scheme.
- If you pulse nCONFIG low for reconfiguration, ensure that the nSTATUS acknowledges nCONFIG. If nSTATUS does not follow the nCONFIG signal, the FPGA may not exit power on reset state. You may need to power cycle the PCB.
- Ensure no external component drives the nSTATUS signal low during the power up.
Did you find the information on this page useful?