5G LDPC-V Intel® FPGA IP User Guide

ID 683670
Date 4/01/2024
Document Table of Contents

2.1.2. 5G LDPC-V IP Timeout Behavior

All IP in a device time out simultaneously when the most restrictive evaluation time is reached. If a design has more than one IP, the time-out behavior of the other IP may mask the time-out behavior of a specific IP .

For IP, the untethered time-out is 1 hour; the tethered time-out value is indefinite. Your design stops working after the hardware evaluation time expires. The Quartus Prime software uses Intel® FPGA IP Evaluation Mode Files (.ocp) in your project directory to identify your use of the Intel® FPGA IP Evaluation Mode evaluation program. After you activate the feature, do not delete these files.

When the evaluation time expires, for the transmitter o_source_data goes low; for the receiver o_source_data and o_ldpc_metrics go low.