5G LDPC-V Intel® FPGA IP User Guide

ID 683670
Date 4/01/2024
Document Table of Contents

1. About the 5G LDPC-V Intel® FPGA IP

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 5.0.3
Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy channels. The 5G LDPC-V Intel® FPGA IP implements LDPC codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration in your wireless design. LDPC codes offer better spectral efficiency than Turbo codes and support the high throughput for 5G new radio (NR).

The 5G LDPC-V IP is a complete channel coding IP that is optimized for virtual radio access networks (vRAN). The 5G LDPC-V IP is based on the 5G LDPC Intel® FPGA IP and includes a 5G NR LDPC channel coder, which comprises:

  • LDPC code block segmentation CRC module
  • LDPC encoder and decoder
  • LDPC rate matcher and derate matcher
  • Hybrid automatic repeat request (HARQ) block (decoder only)
Figure 1. 5G LDPC-V IP

The 5G LDPC-V IP includes the 5G LDPC-V Lite option for reduced resource utilization.