5G LDPC-V Intel® FPGA IP User Guide

ID 683670
Date 3/30/2022

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Document Table of Contents

4.1. 5G LDPC-V Transmitter Functional Description

The LDPC code block segmentation CRC module attaches the CRC for each code block and inserts null bit. For more information, refer to 3GPP TS 38.212. Also, the LDPC code block segmentation CRC module controls its input pace.

The LDPC encoder takes code block data from LDPC code block segmentation CRC module and produces the encoded code block LDPC for the rate matcher.

The LDPC rate matcher implements the rate matching processing (refer to 3GPP TS 38.212) and concatenates the rate matched code block for its output.

All the submodules’ interfaces are based on Avalon streaming interface specification.

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