5G LDPC-V Intel® FPGA IP User Guide

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ID 683670
Date 3/30/2022
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Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC-V Intel® FPGA IP 2. Getting Started with the 5G LDPC-V Intel® FPGA IP 3. Designing with the 5G LDPC-V Intel® FPGA IP 4. 5G LDPC-V Intel® FPGA IP Functional Description 5. 5G LPDC-V IP User Guide Archive 6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide
1. About the 5G LDPC-V Intel® FPGA IP x
1.1. 5G LDPC-V Intel® FPGA IP Features 1.2. 5G LDPC-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G LDPC-V Intel® FPGA IP 1.4. 5G LDPC-V Performance and Resource Utilization
2. Getting Started with the 5G LDPC-V Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC-V IP Timeout Behavior
3. Designing with the 5G LDPC-V Intel® FPGA IP x
3.1. 5G LDPC-V IP Directory Structure 3.2. Generating a 5G LPDC-V IP 3.3. Simulating the 5G LDPC-V IP 3.4. 5G LDPC-V Simulation Results
3.2. Generating a 5G LPDC-V IP x
3.2.1. 5G LDPC-V IP Parameters
4. 5G LDPC-V Intel® FPGA IP Functional Description x
4.1. 5G LDPC-V Transmitter Functional Description 4.2. 5G LDPC-V Receiver Functional Description 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.4. 5G LDPC-V Throughput and Latency
4.1. 5G LDPC-V Transmitter Functional Description x
4.1.1. 5G LDPC-V Transmitter Signals 4.1.2. 5G LDPC-V Lifting Factor and Code Rate Indexes
4.2. 5G LDPC-V Receiver Functional Description x
4.2.1. 5G LDPC-V Receiver Signals
1. About the 5G LDPC-V Intel® FPGA IP
2. Getting Started with the 5G LDPC-V Intel® FPGA IP
3. Designing with the 5G LDPC-V Intel® FPGA IP
4. 5G LDPC-V Intel® FPGA IP Functional Description
5. 5G LPDC-V IP User Guide Archive
6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide

1.3. Release Information for the 5G LDPC-V Intel® FPGA IP

Intel® FPGA IP versions match the Intel® Quartus® Prime Design Suite software versions until v19.1. Starting in Intel® Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.

The Intel® FPGA IP version (X.Y.Z) number can change with each Intel® Quartus® Prime software version. A change in:

  • X indicates a major revision of the IP. If you update the Intel® Quartus® Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Table 1.   5G LDPC-V IP Release Information
Item Description
Version 3.0.0
Release Date June 2021
Level Two Title