5G LDPC-V Intel® FPGA IP User Guide

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ID 683670
Date 3/30/2022
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Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC-V Intel® FPGA IP 2. Getting Started with the 5G LDPC-V Intel® FPGA IP 3. Designing with the 5G LDPC-V Intel® FPGA IP 4. 5G LDPC-V Intel® FPGA IP Functional Description 5. 5G LPDC-V IP User Guide Archive 6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide
1. About the 5G LDPC-V Intel® FPGA IP x
1.1. 5G LDPC-V Intel® FPGA IP Features 1.2. 5G LDPC-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G LDPC-V Intel® FPGA IP 1.4. 5G LDPC-V Performance and Resource Utilization
2. Getting Started with the 5G LDPC-V Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC-V IP Timeout Behavior
3. Designing with the 5G LDPC-V Intel® FPGA IP x
3.1. 5G LDPC-V IP Directory Structure 3.2. Generating a 5G LPDC-V IP 3.3. Simulating the 5G LDPC-V IP 3.4. 5G LDPC-V Simulation Results
3.2. Generating a 5G LPDC-V IP x
3.2.1. 5G LDPC-V IP Parameters
4. 5G LDPC-V Intel® FPGA IP Functional Description x
4.1. 5G LDPC-V Transmitter Functional Description 4.2. 5G LDPC-V Receiver Functional Description 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.4. 5G LDPC-V Throughput and Latency
4.1. 5G LDPC-V Transmitter Functional Description x
4.1.1. 5G LDPC-V Transmitter Signals 4.1.2. 5G LDPC-V Lifting Factor and Code Rate Indexes
4.2. 5G LDPC-V Receiver Functional Description x
4.2.1. 5G LDPC-V Receiver Signals
1. About the 5G LDPC-V Intel® FPGA IP
2. Getting Started with the 5G LDPC-V Intel® FPGA IP
3. Designing with the 5G LDPC-V Intel® FPGA IP
4. 5G LDPC-V Intel® FPGA IP Functional Description
5. 5G LPDC-V IP User Guide Archive
6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide

3.3. Simulating the 5G LDPC-V IP

Verify that the RTL behaves the same as these models.
Before simulating, generate a 5G LDPC-V design example.
  1. Simulate the transmitter with the C-model:
    1. Go to the c_model\ directory.
    2. Compile the C code of the transmitter chain.
      >> gcc -lm ldpc5g_tx_chain_test.c -o run_tx
    3. Run the executable.
      The C program takes three arguments, where the first is the starting test case index, second is the number of test cases, and the third is enabling or disenabling HARQ. For example, the command run_tx 10 15 1 generates test cases from the 10th to the 25th with HARQ enabled.
      The executable generates tx_param.txt tx_in.txt, and tx_out.txt.
  2. Simulate the receiver with the C-model (always simulate the transmitter before you simulate the receiver and with the same arguments):
    1. Go to the c_model\ directory.
    2. Compile the C code of the receiver chain.
      >> g++ -lm ldpc5g_rx_chain_test.cpp -o run_rx
    3. Run the executable.
      The C program takes three arguments, where the first is the starting test case index, second is the number of test cases, and the third is enabling or disenabling HARQ. For example, the command run_rx 10 15 1 generates test cases from the 10th to the 25th with HARQ enabled.

      The executable takes tx_out.txt and generates rx_in.txt, rx_param.txt, and rx_out.txt.

  3. Simulate with the VCS simulator:
    1. Modify these files, if you want to see the waveform of the top level design:
      • For the transmitter, in <Example Design Directory>\src\ldpcv5g_tx_top_tb.sv uncomment the following lines:
        • // Dump waveform, may not work with your simulator
        • $vcdplusfile("./tx.vpd");
        • $vcdplusmemon();
        • $vcdpluson();
      • For the receiver, in <Example Design Directory>\src\ldpcv5g_rx_top_tb.sv uncomment the following lines:
        • // Dump waveform, may not work with your simulator
        • $vcdplusfile("./rx.vpd");
        • $vcdplusmemon();
        • $vcdpluson();
      • In <Example Design Directory>\simulation_scripts\synopsys\vcs\vcs_setup.sh, modify USER_DEFINED_ELAB_OPTIONS="-debug_access+r"
    2. Run vcs_setup.sh from <Example Design Directory>\simulation_scripts\synopsys\vcs\. 
      >> source vcs_setup.sh 
>> simv
      For other simulators (Aldec, Cadence, Mentor or Synopsys), run the script from the corresponding simulator directory in <Example Design Directory>\simulation_scripts\.
  4. Simulate 5G LDPC-V IP with the MATLAB model:
    1. In MATLAB, run make.m from the \matlab\ directory.
      >> make
      MATLAB generates MEX.
    2. Check if p_mat/ exists in matlab/, if not, copy it from ../c_model/p_mat/ in the /matlab/ directory.
    3. Run ldpc5g_txrx_chain_test.m, which is an example testbench to call the transmitter MATLAB function (ldpc5g_tx_chain.m) and receiver MATLAB function (ldpc5g_rx_chain.m).
      >> ldpc5g_txrx_chain_test
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