Putting Altera MAX Series in Hibernation Mode Using User Flash Memory

ID 683668
Date 1/14/2016

1.3.3. Timer

You can use the timer to determine the maximum idle time allowed before the supported Altera device is powered down. Timer is a counter in which the most significant bit (MSB) signal is used to trigger the process of saving the counter data into the UFM and powering down the supported Altera device.

Figure 3. Wait Timer EquationThe following equation shows how to calculate the wait time where T is wait time, n is the width of the counter, and f is the frequency of the internal oscillator that clocks the counter, typically 5 MHz. The width of the counter determines the wait time.

For a longer wait time, increase the counter's width. The signal from the pushbutton that increments the 4-bit binary up-counter resets the timer and prevents the supported Altera device from being powered down. For this example application, the width of the counter is 26 bits wide, so the wait time is approximately 7 seconds.

You can also implement the timer outside of the supported Altera device using other external components to reduce logic element (LE) usage.