Putting Altera MAX Series in Hibernation Mode Using User Flash Memory

ID 683668
Date 1/14/2016

1.4.2. 16-Bit Binary Slow Counter

The 16-bit binary up-counter is the user application module that counts from 16 bits of zeros to 16 bits of ones. It is triggered upon the first Count signal received after the main controller has fetched the UFM stored counter value and written it to the 4-bit binary up-counter display. After the first Count signal is received, the counter counts to all ones. When a new Count signal is received, the counter resets all zeros and resumes counting again. The Reset signal clears the slow counter and waits till a new Count signal is received before counting again.

When the 16-bit slow counter reaches the maximum value, it sends a signal to the main controller to begin the shut-down sequence of fetching the current counter value from the 4-bit binary up-counter, storing it in the UFM, and asserting pwr_dn_ready signal which shuts down the power supply to the device as shown in the Modules in the MAX 10 Design figure.

The 16-bit slow counter, as shown in the Modules in the MAX 10 Design figure, is clocked by the internal oscillator, which can operate up to a maximum frequency of 116 MHz in the 10M08 device used in this design example. The 16-bit resolution is used to make simulation time short, but in real-time operation, this counter will reach the maximum count value in a fraction of a second (2^16*8.62 ns), which is not ideal for testing on an evaluation kit. Everytime you press the Count button, the device would power off before you could press it again.

To change the design for board-level testing, replace the design file ./core/slow_counter.v with the alternate design file provided ./core/slow_counter_30bit.v to be used in the .qsf assignments for compilation. This will increase the number of bits used to an acceptable value for real-time operation. A counter of 30-bits will extend the slow counter to take approximately 9 seconds before issuing a shut-down request.