Quartus® Prime Pro Edition User Guide: Design Optimization

Download PDF
ID 683641
Date 7/08/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Design Optimization Overview 2. Optimizing the Design Netlist 3. Netlist Optimizations and Physical Synthesis 4. Area Optimization 5. Timing Closure and Optimization 6. Analyzing and Optimizing the Design Floorplan 7. Using the ECO Compilation Flow 8. Quartus® Prime Pro Edition Design Optimization User Guide Archives A. Quartus® Prime Pro Edition User Guides
1. Design Optimization Overview x
1.1. Initial FPGA Device Considerations 1.2. Initial Compiler Settings 1.3. Optimization Trade-Offs and Limitations 1.4. Design Visualization and Optimization Tools 1.5. Design Optimization Overview Revision History
1.1. Initial FPGA Device Considerations x
1.1.1. Device Migration Considerations
1.2. Initial Compiler Settings x
1.2.1. Initial I/O Assignment Guidelines 1.2.2. Initial Timing Constraint Guidelines
1.3. Optimization Trade-Offs and Limitations x
1.3.1. Area Reduction Trade-Offs 1.3.2. Critical Path Delay Reduction Trade-Offs 1.3.3. Power Consumption Reduction Trade-Offs 1.3.4. Compilation Time Trade-Offs
1.4. Design Visualization and Optimization Tools x
1.4.1. Design Visualization Tools 1.4.2. Design Optimization Tools
2. Optimizing the Design Netlist x
2.1. When to Use the Netlist Viewers: Analyzing Design Problems 2.2. Quartus® Prime Design Flow with the Netlist Viewers 2.3. RTL Viewer Overview 2.4. Technology Map Viewer Overview 2.5. Netlist Viewer User Interface 2.6. Schematic View 2.7. Cross-Probing to a Source Design File and Other Quartus® Prime Windows 2.8. Cross-Probing to the Netlist Viewers from Other Quartus® Prime Windows 2.9. Viewing a Timing Path 2.10. Optimizing the Design Netlist Revision History
2.3. RTL Viewer Overview x
2.3.1. Maximizing Readability in RTL Viewer 2.3.2. Running the RTL Viewer
2.5. Netlist Viewer User Interface x
2.5.1. Netlist Navigator Pane 2.5.2. Properties Pane 2.5.3. Netlist Viewers Find Pane
2.6. Schematic View x
2.6.1. Display Schematics in Multiple Tabbed View 2.6.2. Schematic Symbols 2.6.3. Select Items in the Schematic View 2.6.4. Shortcut Menu Commands in the Schematic View 2.6.5. Filtering in the Schematic View 2.6.6. View Contents of Nodes in the Schematic View 2.6.7. Moving Nodes in the Schematic View 2.6.8. View LUT Representations in the Technology Map Viewer 2.6.9. Zoom Controls 2.6.10. Navigating with the Bird's Eye View 2.6.11. Partition the Schematic into Pages 2.6.12. Follow Nets Across Schematic Pages
3. Netlist Optimizations and Physical Synthesis x
3.1. Physical Synthesis Optimizations 3.2. Applying Netlist Optimizations 3.3. Scripting Support 3.4. Netlist Optimizations and Physical Synthesis Revision History
3.1. Physical Synthesis Optimizations x
3.1.1. Disabling or Enabling Physical Synthesis Optimization 3.1.2. Physical Synthesis Options
3.2. Applying Netlist Optimizations x
3.2.1. WYSIWYG Primitive Resynthesis
3.3. Scripting Support x
3.3.1. Synthesis Netlist Optimizations 3.3.2. Physical Synthesis Optimizations
4. Area Optimization x
4.1. Resource Utilization Information 4.2. Optimizing Resource Utilization 4.3. Scripting Support 4.4. Area Optimization Revision History
4.1. Resource Utilization Information x
4.1.1. Flow Summary Report 4.1.2. Fitter Reports 4.1.3. Design Assistant Recommendations 4.1.4. Analysis and Synthesis Reports 4.1.5. Compilation Messages 4.1.6. Chip Planner Visualization
4.1.2. Fitter Reports x
4.1.2.1. Route Stage Reports
4.1.2.1. Route Stage Reports x
4.1.2.1.1. Nets with Highest Wire Count Report 4.1.2.1.2. Delay Chain Summary Report 4.1.2.1.3. Top Congested Hierarchies and Nets Reports 4.1.2.1.4. Global Route Reports
4.2. Optimizing Resource Utilization x
4.2.1. Resource Utilization Issues Overview 4.2.2. I/O Pin Utilization or Placement 4.2.3. Logic Utilization or Placement 4.2.4. Routing
4.2.2. I/O Pin Utilization or Placement x
4.2.2.1. Guideline: Modify Pin Assignments or Choose a Larger Package
4.2.3. Logic Utilization or Placement x
4.2.3.1. Guideline: Optimize Source Code 4.2.3.2. Guideline: Optimize Synthesis for Area, Not Speed 4.2.3.3. Guideline: Restructure Multiplexers 4.2.3.4. Guideline: Perform WYSIWYG Primitive Resynthesis with Balanced or Area Setting 4.2.3.5. Guideline: Use Register Packing 4.2.3.6. Guideline: Remove Fitter Constraints 4.2.3.7. Guideline: Flatten the Hierarchy During Synthesis 4.2.3.8. Guideline: Re-target Memory Blocks 4.2.3.9. Guideline: Use Physical Synthesis Options to Reduce Area 4.2.3.10. Guideline: Retarget or Balance DSP Blocks 4.2.3.11. Guideline: Use a Larger Device 4.2.3.12. Guideline: Reduce Global Signal Congestion 4.2.3.13. Guideline: Report Pipelining Information
4.2.4. Routing x
4.2.4.1. Guideline: Set Auto Packed Registers to Sparse or Sparse Auto 4.2.4.2. Guideline: Set Fitter Aggressive Routability Optimizations to Always 4.2.4.3. Guideline: Increase Router Effort Multiplier 4.2.4.4. Guideline: Remove Fitter Constraints 4.2.4.5. Guideline: Optimize Synthesis for Routability 4.2.4.6. Guideline: Optimize Source Code 4.2.4.7. Guideline: Use a Larger Device
4.3. Scripting Support x
4.3.1. Initial Compilation Settings 4.3.2. Resource Utilization Optimization Techniques
5. Timing Closure and Optimization x
5.1. Optimize Multi Corner Timing 5.2. Optimize Critical Paths 5.3. Optimize Critical Chains 5.4. Design Evaluation for Timing Closure 5.5. Timing Optimization 5.6. Periphery to Core Register Placement and Routing Optimization 5.7. Scripting Support 5.8. Timing Closure and Optimization Revision History
5.2. Optimize Critical Paths x
5.2.1. Viewing Critical Paths
5.3. Optimize Critical Chains x
5.3.1. Viewing Critical Chains
5.4. Design Evaluation for Timing Closure x
5.4.1. Review Messages 5.4.2. Evaluate Fitter Netlist Optimizations 5.4.3. Evaluate Optimization Results 5.4.4. Evaluate Resource Usage 5.4.5. Evaluate Other Reports and Adjust Settings Accordingly 5.4.6. Evaluate Clustering Difficulty 5.4.7. Revise and Recompile
5.4.4. Evaluate Resource Usage x
5.4.4.1. Evaluate Global and Non-Global Usage 5.4.4.2. Evaluate Routing Usage 5.4.4.3. Evaluate Wires Added for Hold
5.5. Timing Optimization x
5.5.1. Correct Design Assistant Rule Violations 5.5.2. Implement Fast Forward Timing Closure Recommendations 5.5.3. Review Timing Path Details 5.5.4. Try Optional Fitter Settings 5.5.5. Back-Annotating Optimized Assignments 5.5.6. Optimize Settings with Design Space Explorer II 5.5.7. Aggregating and Comparing Compilation Results with Exploration Dashboard 5.5.8. I/O Timing Optimization Techniques 5.5.9. Register-to-Register Timing Optimization Techniques 5.5.10. Metastability Analysis and Optimization Techniques
5.5.2. Implement Fast Forward Timing Closure Recommendations x
5.5.2.1. Retiming Limit Details Report 5.5.2.2. Fast Forward Timing Closure Recommendations
5.5.2.1. Retiming Limit Details Report x
5.5.2.1.1. Using the Retiming Limit Details Report
5.5.2.2. Fast Forward Timing Closure Recommendations x
5.5.2.2.1. Generating Fast Forward Timing Closure Recommendations 5.5.2.2.2. Implementing Fast Forward Recommendations
5.5.3. Review Timing Path Details x
5.5.3.1. Report Timing 5.5.3.2. Report Logic Depth 5.5.3.3. Report Neighbor Paths 5.5.3.4. Report Register Spread 5.5.3.5. Report Route Net of Interest 5.5.3.6. Report Retiming Restrictions 5.5.3.7. Report Pipelining Information 5.5.3.8. Report CDC Viewer 5.5.3.9. Timing Closure Recommendations 5.5.3.10. Global Network Buffers 5.5.3.11. Resets and Global Networks 5.5.3.12. Suspicious Setup 5.5.3.13. Auto Shift Register Replacement 5.5.3.14. Clocking Architecture
5.5.3.10. Global Network Buffers x
5.5.3.10.1. Source Location 5.5.3.10.2. Insertion Delay 5.5.3.10.3. Fan-Out 5.5.3.10.4. Global Signal Assignment
5.5.4. Try Optional Fitter Settings x
5.5.4.1. Optimize Hold Timing 5.5.4.2. Fitter Aggressive Routability Optimization
5.5.6. Optimize Settings with Design Space Explorer II x
5.5.6.1. DSE II Computing Resources 5.5.6.2. DSE II Optimization Parameters 5.5.6.3. DSE II Result Management 5.5.6.4. Running DSE II
5.5.7. Aggregating and Comparing Compilation Results with Exploration Dashboard x
5.5.7.1. Aggregation Use Case 5.5.7.2. Comparison Use Case 5.5.7.3. Exploration Dashboard Object-Property Model 5.5.7.4. Starting the Exploration Dashboard
5.5.7.3. Exploration Dashboard Object-Property Model x
5.5.7.3.1. Base Exploration Dashboard Properties 5.5.7.3.2. Project Handle Properties 5.5.7.3.3. Project Group Objects and Properties 5.5.7.3.4. Workspace Objects and Properties
5.5.8. I/O Timing Optimization Techniques x
5.5.8.1. I/O Timing Constraints 5.5.8.2. Optimize IOC Register Placement for Timing Logic Option 5.5.8.3. Fast Input, Output, and Output Enable Registers 5.5.8.4. Programmable Delays 5.5.8.5. Use PLLs to Shift Clock Edges 5.5.8.6. Use Fast Regional Clock Networks and Regional Clocks Networks 5.5.8.7. Spine Clock Limitations
5.5.9. Register-to-Register Timing Optimization Techniques x
5.5.9.1. Optimize Source Code 5.5.9.2. Improving Register-to-Register Timing 5.5.9.3. Physical Synthesis Optimizations 5.5.9.4. Set Power Optimization During Synthesis to Normal Compilation 5.5.9.5. Optimize Synthesis for Performance, Not Area 5.5.9.6. Flatten the Hierarchy During Synthesis 5.5.9.7. Set the Synthesis Effort to High 5.5.9.8. Change Adder Tree Styles 5.5.9.9. Duplicate Registers for Fan-Out Control 5.5.9.10. Prevent Shift Register Inference 5.5.9.11. Use Other Synthesis Options Available in Your Synthesis Tool 5.5.9.12. Fitter Seed 5.5.9.13. Set Maximum Router Timing Optimization Level 5.5.9.14. Register-to-Register Timing Analysis
5.5.9.9. Duplicate Registers for Fan-Out Control x
5.5.9.9.1. Manual Register Duplication 5.5.9.9.2. Automatic Register Duplication: Estimated Physical Proximity 5.5.9.9.3. Automatic Register Duplication: Hierarchical Proximity
5.5.9.14. Register-to-Register Timing Analysis x
5.5.9.14.1. Tips for Analyzing Failing Paths 5.5.9.14.2. Tips for Analyzing Failing Clock Paths that Cross Clock Domains 5.5.9.14.3. Tips for Critical Path Analysis 5.5.9.14.4. Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles 5.5.9.14.5. Global Routing Resources 5.5.9.14.6. Register RAMS and DSPs
5.6. Periphery to Core Register Placement and Routing Optimization x
5.6.1. Setting Periphery to Core Optimizations in the Advanced Fitter Setting Dialog Box 5.6.2. Setting Periphery to Core Optimizations in the Assignment Editor 5.6.3. Viewing Periphery to Core Optimizations in the Fitter Report
5.7. Scripting Support x
5.7.1. Initial Compilation Settings 5.7.2. I/O Timing Optimization Techniques 5.7.3. Register-to-Register Timing Optimization Techniques
6. Analyzing and Optimizing the Design Floorplan x
6.1. Location Assignment Optimization Guidelines 6.2. Design Floorplan Analysis in Chip Planner 6.3. Defining Logic Lock Placement Constraints 6.4. Defining Virtual Pins 6.5. Using Logic Lock Regions in Combination with Design Partitions 6.6. Creating Clock Region Assignments in Chip Planner 6.7. Scripting Support 6.8. Analyzing and Optimizing the Design Floorplan Revision History
6.2. Design Floorplan Analysis in Chip Planner x
6.2.1. Starting the Chip Planner 6.2.2. Chip Planner GUI 6.2.3. Viewing Design Elements in Chip Planner 6.2.4. Finding Design Elements in the Chip Planner 6.2.5. Exploring Paths in the Chip Planner 6.2.6. Viewing Assignments in the Chip Planner 6.2.7. Viewing High-Speed and Low-Power Tiles in the Chip Planner 6.2.8. Viewing Design Partition Placement
6.2.3. Viewing Design Elements in Chip Planner x
6.2.3.1. Viewing Architecture-Specific Design Information in Chip Planner 6.2.3.2. Viewing Available Clock Networks in Chip Planner 6.2.3.3. Viewing Clock Sector Utilization in Chip Planner 6.2.3.4. Viewing Routing Congestion in Chip Planner 6.2.3.5. Viewing I/O Banks in Chip Planner 6.2.3.6. Viewing High-Speed Serial Interfaces (HSSI) in Chip Planner 6.2.3.7. Viewing Source and Destination Nodes in Chip Planner 6.2.3.8. Viewing Fan-In and Fan-Out in Chip Planner 6.2.3.9. Viewing Immediate Fan-In and Fan-Out in Chip Planner 6.2.3.10. Viewing the Selected Contents in Chip Planner 6.2.3.11. Viewing the Location and Utilization of Device Resources in Chip Planner 6.2.3.12. Viewing Module Placement by Cross-Probing to Chip Planner
6.2.3.4. Viewing Routing Congestion in Chip Planner x
6.2.3.4.1. Areas with Routing Congestion 6.2.3.4.2. Congestion due to HDL Coding style
6.2.4. Finding Design Elements in the Chip Planner x
6.2.4.1. Find Options (Chip Planner Search)
6.2.5. Exploring Paths in the Chip Planner x
6.2.5.1. Analyzing Connections for a Path 6.2.5.2. Locate Path from the Timing Analysis Report to the Chip Planner 6.2.5.3. Show Delays 6.2.5.4. Viewing Routing Resources
6.3. Defining Logic Lock Placement Constraints x
6.3.1. The Logic Lock Regions Window 6.3.2. Defining Logic Lock Regions 6.3.3. Customizing the Shape of Logic Lock Regions 6.3.4. Assigning Device Pins to Logic Lock Regions 6.3.5. Viewing Connections Between Logic Lock Regions in Chip Planner 6.3.6. Example: Placement Best Practices for Arria® 10 FPGAs 6.3.7. Migrating Assignments between Quartus® Prime Standard Edition and Quartus® Prime Pro Edition
6.3.2. Defining Logic Lock Regions x
6.3.2.1. Defining a Logic Lock Region in Chip Planner 6.3.2.2. Defining a Logic Lock Region from the Project Navigator 6.3.2.3. Defining Routing Regions 6.3.2.4. Defining Empty Logic Lock Regions 6.3.2.5. Defining Hierarchical Logic Lock Regions
6.3.2.1. Defining a Logic Lock Region in Chip Planner x
6.3.2.1.1. Logic Lock Region Properties 6.3.2.1.2. Snapping to a Region 6.3.2.1.3. Considerations for Auto Sized Regions
6.3.3. Customizing the Shape of Logic Lock Regions x
6.3.3.1. Adding a New Shape to a Logic Lock Region 6.3.3.2. Subtracting Shape from Logic Lock Region 6.3.3.3. Merging Logic Lock Regions 6.3.3.4. Defining Noncontiguous Logic Lock Regions
6.5. Using Logic Lock Regions in Combination with Design Partitions x
6.5.1. Viewing Design Connectivity and Hierarchy
6.6. Creating Clock Region Assignments in Chip Planner x
6.6.1. Creating Clock Assignments in Chip Planner 6.6.2. Resizing a Clock Assignment in Chip Planner 6.6.3. Moving a Clock Assignment in Chip Planner 6.6.4. Deleting a Clock Region Assignment in Chip Planner 6.6.5. Assigning a Clock Signal to a Clock Region in Chip Planner
6.6.1. Creating Clock Assignments in Chip Planner x
6.6.1.1. Clock Assignment Properties
6.7. Scripting Support x
6.7.1. Creating Logic Lock Assignments with Tcl commands 6.7.2. Assigning Virtual Pins with a Tcl command 6.7.3. Logic Lock Region Assignment Examples
7. Using the ECO Compilation Flow x
7.1. ECO Compilation Flow 7.2. ECO Tcl Script Example 7.3. Viewing ECO Compilation Reports 7.4. ECO Commands 7.5. ECO Command Limitations 7.6. Interactive ECO Fitting 7.7. Using the ECO Compilation Flow Revision History
7.4. ECO Commands x
7.4.1. ECO Command Quick Reference 7.4.2. make_connection 7.4.3. remove_connection 7.4.4. modify_lutmask 7.4.5. adjust_pll_refclk 7.4.6. modify_io_slew_rate 7.4.7. modify_io_current_strength 7.4.8. modify_io_delay_chain 7.4.9. create_new_node 7.4.10. remove_node 7.4.11. place_node 7.4.12. unplace_node 7.4.13. create_wirelut
7.6. Interactive ECO Fitting x
7.6.1. eco_load_design and eco_commit_design Commands
Answers to Top FAQs
1. Design Optimization Overview
2. Optimizing the Design Netlist
3. Netlist Optimizations and Physical Synthesis
4. Area Optimization
5. Timing Closure and Optimization
6. Analyzing and Optimizing the Design Floorplan
7. Using the ECO Compilation Flow
8. Quartus® Prime Pro Edition Design Optimization User Guide Archives
A. Quartus® Prime Pro Edition User Guides

2.6.2. Schematic Symbols

The symbols for nodes in the schematic represent elements of your design netlist. These elements include input and output ports, registers, logic gates, Intel primitives, high-level operators, and hierarchical instances.
Note: The logic gates and operator primitives appear only in the RTL Viewer. Logic in the Technology Map Viewer is represented by atom primitives, such as registers and LCELLs.
Table 6.  Symbols in the Schematic View This table lists and describes the primitives and basic symbols that you can display in the schematic view of the RTL Viewer and Technology Map Viewer.
Symbol Description

Wire indicator and net ripper

 Indicates the net signal flow direction into or out of the pin or port. There can be symbols in both directions due to automatic net bundling from the connectivity. You can click the net to highlight the signal flow details in the schematic.
I/O Ports

An input, output, or bidirectional port in the current level of hierarchy. A device input, output, or bidirectional pin when viewing the top‑level hierarchy. The symbol can also represent a bus. Only one wire is shown connected to the bidirectional symbol, representing the input and output paths.

Input symbols appear on the left-most side of the schematic. Output and bidirectional symbols appear on the right‑most side of the schematic.

I/O Connectors



 An input or output connector, representing a net that comes from another page of the same hierarchy. To go to the page that contains the source or the destination, double-click the connector to jump to the appropriate page.
OR, AND, XOR Gates





 An OR, AND, or XOR gate primitive (the number of ports can vary). A small circle (bubble symbol) on an input or output port indicates the port is inverted.
MULTIPLEXER

 A multiplexer primitive with a selector port that selects between port 0 and port 1. A multiplexer with more than two inputs is displayed as an operator.
BUFFER

 A buffer primitive. The figure shows the tri-state buffer, with an inverted output enable port. Other buffers without an enable port include LCELL, SOFT, and GLOBAL. The NOT gate and EXP expander buffers use this symbol without an enable port and with an inverted output port.
LATCH

 A latch/DFF (data flipflop) primitive. A DFF has the same ports as a latch and a clock trigger. The other flipflop primitives are similar:
  • DFFEA (data flipflop with enable and asynchronous load) primitive with additional ALOAD asynchronous load and ADATA data signals
  • DFFEAS (data flipflop with enable and synchronous and asynchronous load), which has ASDATA as the secondary data port
Atom Primitive

 An atom primitive. The symbol displays the atom name, the port names, and the atom type. The blue shading indicates an atom primitive for which you can view the internal details.
Other Primitive

 Any primitive that does not fall into the previous categories. Primitives are low-level nodes that cannot be expanded to any lower hierarchy. The symbol displays the port names, the primitive or operator type, and its name.
Instance

 An instance in the design that does not correspond to a primitive or operator (a user‑defined hierarchy block). The symbol displays the port name and the instance name.
Encrypted Instance

 A user-defined encrypted instance in the design. The symbol displays the instance name. You cannot open the schematic for the lower-level hierarchy, because the source design is encrypted.
RAM

 A synchronous memory instance with registered inputs and optionally registered outputs. The symbol shows the device family and the type of memory block. This figure shows a true dual-port memory block in a Stratix M-RAM block.
Constant



 A constant signal value that is highlighted in gray and displayed in hexadecimal format by default throughout the schematic.
Table 7.  Operator Symbols in the RTL Viewer Schematic View     The following lists and describes the additional higher level operator symbols in the RTL Viewer schematic view.
Symbol Description


An adder operator:

OUT = A + B


A multiplier operator:

OUT = A ¥ B



A divider operator:

OUT = A / B


Equals


A left shift operator:

OUT = (A << COUNT)


A right shift operator:

OUT = (A >> COUNT)


A modulo operator:

OUT = (A%B)



A less than comparator:

OUT = (A<:B:A>B)


A multiplexer:

OUT = DATA [SEL]

The data range size is 2sel range size



A selector:

A multiplexer with one-hot select input and more than two input signals



A binary number decoder:

OUT = (binary_number (IN) == x)

for x = 0 to
Related Information
Level Two Title