Nios® V Processor Reference Manual

ID 683632
Date 9/26/2022

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Document Table of Contents

4. Document Revision History for the Nios® V Processor Reference Manual

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.09.26 22.3 22.3.0
  • Updated the values in Table: Nios V/m Processor Performance Benchmarks in Intel FPGA Devices.
  • Replaced Table: Reset and Debug Signals with new signals, types, and descriptions.
  • Updated the step to set exception address in section Exception Controller.
2022.08.01 22.2 21.3.0
  • Edited the performance metric value in Table: Architecture Performance.
  • Added new sections
    • Trigger
    • Typical Use Cases
  • Edited the following sections:
    • Reset and Debug Signals
    • RISC-V based Debug Module
    • Debug Mode
    • Halt from Debug Module
    • Control and Status Registers (CSR) Mapping
    • Control and Status Register Field
2022.06.30 22.1 21.2.0 Added new section Reset and Debug Signals.
2022.03.28 21.4 21.1.1 Updated RISC-V based Debug Module section with details for Nios® V processor.
2021.12.13 21.4 21.1.1 Updated IP version and Intel® Quartus® Prime version.
2021.11.15 21.3 21.1.0 Edited Table: Architecture Performance in Section: Processor Performance Benchmarks.
  • Change CoreMark to CoreMark/MHz Ratio and updated the value to 0.32148.
2021.10.04 21.3 21.1.0 Initial release.