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2.3. Processor Architecture
The Nios® V/m processor architecture describes an instruction-set architecture (ISA). The ISA in turn necessitates a set of functional units that implement the instructions.
The Nios® V/m processor architecture defines the following functional units:
- General-purpose register file
- Arithmetic logic unit (ALU)
- Control and status registers (CSR)
- Exception controller
- Interrupt controller
- Instruction bus
- Data bus
- RISC-V based debug module
Figure 2. Nios® V/m Processor Core Block Diagram
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