F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 6/21/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Round-trip Latency 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Interlaken Look-aside Data Path Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Data Path Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multi-Segment Mode 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multi-Segment Mode x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide

1.3. Performance and Resource Utilization

This section covers the resources and expected performance numbers for selected variations of the Interlaken IP core using the Intel® Quartus® Prime Pro Edition software. Your results may slightly vary depending on the device you select.

For a comprehensive list of supported configurations, refer to Table 1. IP Supported Combinations of Number of Lanes and Data Rates

Table 4.  Resource Utilization for Interleaved ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 22.2.
Device PMA Type Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ F-tile (NRZ) FGT 4 6.25 18632 40950 7874 28
12 10.3125 58460 113120 19280 73
4 12.5 18624 40938 7845 28
8 37979 76393 14122 52
10 48108 94516 16658 61
12 58444 113094 19256 73
4 25.78125 18730 41603 8036 28
6 29736 63854 11819 52
8 38234 77616 14455 52
10 53105 110193 18898 100
12 63149 126609 21906 100
Intel® Agilex™ F-tile (PAM4) 2 53.125 18414 45665 8914 28
2 (with eFIFO) 18697 46006 8947 28
4 37340 84953 16491 52
4 (with eFIFO) 37823 85670 16572 52
6 61383 138963 23707 100
6 (with eFIFO) 62092 139914 24056 100
FHT 1 (with eFIFO) 106.25 18667 46010 9030 28
2 (with eFIFO) 37781 85637 16514 52
3 (with eFIFO) 62085 139489 24405 100
Table 5.  Resource Utilization for Packet ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 22.2.
Device PMA Type Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ F-tile (NRZ) FGT 4 6.25 18639 40867 7820 28
12 10.3125 58454 113161 19084 73
4 12.5 18633 41002 7838 28
8 38018 76503 13947 52
10 48131 94586 16577 61
12 58443 112986 19222 73
4 25.78125 18752 41278 8405 28
6 29702 63760 11922 52
8 38272 77390 14614 52
10 53099 110228 18815 100
12 63204 127048 21665 100
Intel® Agilex™ F-tile (PAM4) 2 53.125 18406 45631 8820 28
2 (with eFIFO) 18661 45932 9045 28
4 37356 84862 16363 52
4 (with eFIFO) 37795 85420 16653 52
6 61375 138892 23710 100
6 (with eFIFO) 62078 140011 24000 100
FHT 1 (with eFIFO) 106.25 18666 45848 9113 28
2 (with eFIFO) 37762 85606 16550 52
3 (with eFIFO) 62001 139467 24295 100
Table 6.  Resource Utilization for Interlaken Look-aside ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 22.2.
Device PMA Type Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ F-tile (NRZ) FGT 4 6.25 13829 30771 5831 0
12 10.3125 44069 82264 15405 0
4 12.5 13844 30660 5983 0
8 28401 55408 10573 0
10 36007 70426 13022 0
12 44056 81899 15826 0
4 25.78125 13846 30780 6110 0
6 20908 43063 8729 0
8 28324 55602 10964 0
10 36017 70264 13749 0
12 44037 82297 16029 0
Intel® Agilex™ F-tile (PAM4) 2 53.125 13369 34983 6673 0
2 (with eFIFO) 13631 35322 6897 0
4 27386 62604 13065 0
4 (with eFIFO) 27868 641147 12724 0
6 42463 93753 18456 0
6 (with eFIFO) 43290 94677 18963 0
FHT 1 (with eFIFO) 106.25 13610 35249 6891 0
2 (with eFIFO) 27800 63668 13035 0
3 (with eFIFO) 43246 94469 19108 0
Level Two Title