F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 6/21/2022
Public

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Document Table of Contents

8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.06.21 22.2 4.1.0
  • Added the FHT PMA support for PAM4 variants.
  • Updated the sections with FHT PMA information: Features and System PLL Configuration.
  • Updated the Resource Utilization and Round-trip Latency numbers.
  • Added information about the IP-XACT file generation in section: Specifying the IP Core Parameters and Options.
  • Added note for Enable EFIFO support.
  • Added signal availability for Interlaken and Interlaken Look-aside mode in section: Interface Signals.
2022.03.28 22.1 4.0.0
  • Added support for the Interlaken Look-aside mode for all variants.
  • Updated the Resource Utilization numbers.
  • Removed support for the ModelSim* SE simulator.
2022.01.14 21.4 3.1.0
  • Added support for the Cadence* Xcelium* simulator.
  • Added support for the Interlaken Look-aside mode for three variants:
    • 6 x 53.125G
    • 12 x 12.5G
    • 12 x 25.78125G
  • Added support for new lane rate combinations. For more information, refer to Table: IP Supported Combinations of Number of Lanes and Data Rate.
  • Updated the Resource Utilization numbers.
  • Added new parameters:
    • Enable Interlaken Look-aside mode
    • Enable debug endpoint for Datapath and PMA Avalon® memory-mapped interface
2021.10.04 21.3 3.0.0
  • Added support for new lane rate combinations. For more information, refer to Table: IP Supported Combinations of Number of Lanes and Data Rate.
  • Updated the reset signals in sections: IP Reset and Clock and Reset Interface Signals.
2021.06.21 21.2 2.0.0 Initial release.