F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 6/21/2022
Public

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2.4.1. System PLL Configuration

For Interlaken, the NRZ mode is supported without FEC while the PAM4 mode is supported with FEC.

Instantiate the F-Tile Reference and System PLL Clocks Intel FPGA IP for your F-Tile Interlaken Intel® FPGA IP design with the following parameters:
Table 11.  System PLL IP Parameters
Parameters Value for NRZ Mode Value for PAM4 Mode (FGT) Value for PAM4 Mode (FHT)
Mode of System PLL

(syspll_mod_<m>)

User Configuration 2 User Configuration User Configuration
Refclk source

(syspll_refclk_src_<m>)

RefClk #<n> RefClk #<n> RefClk #<n>
Output frequency

(syspll_freq_mhz_<m>)

Any frequency2

Without eFIFO: 830.078125 MHz

With eFIFO: Frequency selected from user interface parameter (System PLL clock frequency).

Frequency selected from user interface parameter (System PLL clock frequency).
Enable Refclk #<n> for FGT PMA

(refclk_fgt_output_enable_<n>)

Yes Yes -
Enable FHT Common PLL <n> for FHT PMA

(cmnpll_enable_<n>)

- - Yes
Refclk frequency #<n>

(refclk_fgt_freq_mhz_<n>)

User desired refclk frequency 3 User desired refclk frequency3 -
Refclk frequency #<n>

(refclk_fht_freq_mhz_txt_<n>)

- - User desired refclk frequency3
System PLL Output Enable <n>

(systempll_output_enable_<n>)

- Yes Yes
Figure 5. Port Connection between F-Tile Reference and System PLL Clocks Intel FPGA IP and F-Tile Interlaken Intel® FPGA IP
2 This is a mandatory requirement for each F-tile if there is no other system in use.
3 The frequency must be the same as the reference clock set in F-Tile Interlaken Intel® FPGA IP.