F-Tile Interlaken Intel® FPGA IP User Guide

Download PDF
ID 683622
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Round-trip Latency 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Interlaken Look-aside Data Path Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Data Path Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multi-Segment Mode 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multi-Segment Mode x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Examples
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide

1.3. Performance and Resource Utilization

This section covers the resources and expected performance numbers for selected variations of the Interlaken IP core using the Intel® Quartus® Prime Pro Edition software. Your results may slightly vary depending on the device you select.

For a comprehensive list of supported configurations, refer to Table 1. IP Supported Combinations of Number of Lanes and Data Rates

Table 4.  Resource Utilization for Interleaved ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 22.1.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ F-tile (NRZ) 4 6.25 18136 43012 8060 28
12 10.3125 58326 114677 19809 73
4 12.5 18126 43106 7928 28
8 37854 78396 14193 52
10 47984 96244 16969 61
12 58377 114492 20001 73
4 25.78125 18281 43528 8406 28
6 29598 65673 12068 52
8 38185 79508 14714 52
10 52961 112058 19022 100
12 63078 128963 21699 100
Intel® Agilex™ F-tile (PAM4) 2 53.125 17890 47705 9031 28
2 (with eFIFO) 18166 48162 9133 28
4 37163 87176 16193 52
4 (with eFIFO) 37654 87733 16652 52
6 60898 140077 24548 100
6 (with eFIFO) 61688 141840 24225 100
Table 5.  Resource Utilization for Packet ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 22.1.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ F-tile (NRZ) 4 6.25 18131 42922 8228 28
12 10.3125 58331 114975 19477 73
4 12.5 18128 43140 7927 28
8 37902 78571 14175 52
10 47919 96429 16882 61
12 58295 114519 19986 73
4 25.78125 18271 43484 8557 28
6 29551 65771 12003 52
8 38158 79366 14809 52
10 53030 111985 19105 100
12 62987 128990 21744 100
Intel® Agilex™ F-tile (PAM4) 2 53.125 17884 47808 9012 28
2 (with eFIFO) 18132 48151 9148 28
4 37149 87105 16331 52
4 (with eFIFO) 37671 87586 16708 52
6 60920 140673 23876 100
6 (with eFIFO) 61633 141410 24470 100
Table 6.  Resource Utilization for Interlaken Look-aside ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 22.1.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ F-tile (NRZ) 4 6.25 13534 32568 5873 0
12 10.3125 43861 83501 15785 0
4 12.5 13498 32522 5934 0
8 27935 57013 10736 0
10 35651 71836 13163 0
12 43927 83462 15969 0
4 25.78125 13498 32578 6010 0
6 20500 44800 8678 0
8 27949 57116 11125 0
10 35694 71863 13947 0
12 43843 83436 16112 0
Intel® Agilex™ F-tile (PAM4) 2 53.125 13067 36690 6834 0
2 (with eFIFO) 13229 36953 7042 0
4 27186 64889 12623 0
4 (with eFIFO) 27678 65475 12855 0
6 42241 95593 18417 0
6 (with eFIFO) 42926 96232 18969 0
Level Two Title