F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Round-trip Latency 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Interlaken Look-aside Data Path Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Data Path Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multi-Segment Mode 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multi-Segment Mode x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Examples
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide

1.1. Features

The F-Tile Interlaken Intel® FPGA IP core supports the following features:
  • General features:
    • Compliant with the Interlaken Protocol Specification, Revision 1.2.
    • Compliant with the Interlaken Reed-Solomon Forward Error Correction (RS-FEC) Extension Specification, Revision 1.1.
    • Supports 2, 4, 6, 8, 10, and 12 serial lanes in configurations that provide up to 318.75 Gbps raw bandwidth. Refer to the Table: IP Supported Combinations of Number of Lanes and Data Rates below for more details on current list of supported configurations.
    • Supports per-lane data rates of 6.25, 10.3125, 12.5, 25.78125, and 53.125 Gbps using Intel FPGA on-chip high-speed transceivers.
    • All variants support the Interlaken Look-aside Mode.
  • User interface features:
    • Supports dynamically configurable BurstMax and BurstMin values.
    • Supports Packet mode and Interleaved mode for user data transfer.
    • Supports up to 256 logical channels in out-of-the-box configuration.
    • Supports multi-segment user interface.
  • Flow-control features:
    • Supports optional out-of-band flow control blocks.
    • Supports optional user-controlled in-band flow control with 1, 2, 4, 8, or 16 16-bit calendar pages.
    • Supports error correction code (ECC) for memory block implementation with the IP.
  • Line-side features:
    • Supports per-lane data rate of 53.125 Gbps using pulse amplitude modulation (PAM4) mode.
    • Supports per lane data rates of 6.25, 10.3125, 12.5, 25.78125 Gbps using non-return-to-zero (NRZ) mode.
Table 1.  IP Supported Combinations of Number of Lanes and Data RatesThe following combinations are supported in the Intel® Quartus® Prime Pro Edition software version 22.1.
Number of Lanes Lane Rate (Gbps)
6.25 10.3125 12.5 25.78125 53.125
2 - - - - Yes
4 Yes - Yes Yes Yes
6 - - - Yes Yes
8 - - Yes Yes -
101 - - Yes Yes -
12 - Yes Yes Yes -
Table 2.  IP Theoretical Raw Aggregate BandwidthThe following combinations are supported in the Intel® Quartus® Prime Pro Edition software version 22.1.
Lane Rate (Gbps) Number of Lanes User Interface Width (words) Data Width (bits) Raw Aggregate Bandwidth (Gbps)
6.25 4 4 256 25
10.3125 12 8 512 123.75
12.5 4 4 256 50
8 8 512 100
10 8 512 125
12 8 512 150
25.78125 4 4 256 103.125
6 8 512 154.6875
8 8 512 206.25
10 16 1024 257.8125
12 16 1024 309.375
53.125 2 4 256 106.25
4 8 512 212.5
6 16 1024 318.75
1 For a 10-lane configuration design, the F-tile requires 12 lanes of TX PMA to enable bonded transceiver clocking for minimizing the channel skew.
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