Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/02/2023
Public

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Document Table of Contents

7.11.1.1. Avalon® Streaming Data Interface

Each FIFO IP has an Avalon® Streaming data sink and source interface. The data sink and source interfaces in the dual-clock FIFO IP are driven by different clocks.

Table 193.   Avalon® Streaming Interfaces Properties

Feature

Property

Backpressure

Ready latency = 0.

Data Width

Configurable.

Channel

Supported, up to 255 channels.

Error

Configurable.

Packet

Configurable.