Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.5.2.2. Limiting Concurrency

The amount of logic generated for the interconnect often increases as the system becomes larger because Platform Designer creates arbitration logic for every agent interface that is shared by multiple host interfaces. Platform Designer inserts multiplexer logic between host interfaces that connect to multiple agent interfaces if both support read datapaths.

Most embedded processor designs contain components that are either incapable of supporting high data throughput, or do not need to be accessed frequently. These components can contain host or agent interfaces. Because the interconnect supports concurrent accesses, you may want to limit concurrency by inserting bridges into the datapath to limit the amount of arbitration and multiplexer logic generated.

For example, if a system contains three host and three agent interfaces that are interconnected, Platform Designer generates three arbiters and three multiplexers for the read datapath. If these hosts do not require a significant amount of simultaneous throughput, you can reduce the resources that your design consumes by connecting the three hosts to a pipeline bridge. The bridge controls the three agent interfaces and reduces the interconnect into a bus structure. Platform Designer creates one arbitration block between the bridge and the three hosts, and a single read datapath multiplexer between the bridge and three agents, and prevents concurrency. This implementation is similar to a standard bus architecture.

You should not use this method for high throughput datapaths to ensure that you do not limit overall system performance.

Figure 162. Differences Between Systems With and Without a Pipeline Bridge