Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 10/02/2023
Public

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5.9. Reset Polarity and Synchronization in Platform Designer

When you add a component interface with a reset signal, Platform Designer defines its polarity as reset(active-high) or reset_n (active-low).

You can view the polarity status of a reset signal by selecting the signal in the Hierarchy tab, and then view its expanded definition in the open Parameters and Block Symbol tabs. When you generate your component, Platform Designer interconnect automatically inverts polarities as needed.

Figure 179. Reset Signal (Active-High)
Figure 180. Reset Signal Active-Low
Each Platform Designer component has its own requirements for reset synchronization. Some blocks have internal synchronization and have no requirements, whereas other blocks require an externally synchronized reset. You can define how resets are synchronized in your Platform Designer system with the Synchronous edges parameter. In the clock source or reset bridge component, set the value of the Synchronous edges parameter to one of the following, depending on how the reset is externally synchronized:
  • None—There is no synchronization on this reset.
  • Both—The reset is synchronously asserted and deasserted with respect to the input clock.
  • Deassert—The reset is synchronously asserted with respect to the input clock, and asynchronously deasserted.
Figure 181. Synchronous Edges Parameter

You can combine multiple reset sources to reset a particular component.

Figure 182. Combine Multiple Reset Sources

When you generate your component, Platform Designer inserts adapters to synchronize or invert resets if there are mismatches in polarity or synchronization between the source and destination. You can view inserted adapters on the Memory-Mapped Interconnect tab with the System > Show System with Platform Designer Interconnect command.

Figure 183.  Platform Designer Interconnect