AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller

Download PDF
ID 683601
Date 9/22/2017
Public
Document Table of Contents
Document Table of Contents x
1. AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller
1. AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller x
1.1. ULPI Signals 1.2. HPS USB Controller Timing Characteristics 1.3. PHY Selection 1.4. Implementing Input Clock Mode with FPGA Clock Source 1.5. Revision History
1.2. HPS USB Controller Timing Characteristics x
1.2.1. USB Controller Timing Requirements 1.2.2. USB Controller Setup and Hold Relationships
1.3. PHY Selection x
1.3.1. USB PHY Timing Characteristics 1.3.2. Output Clock Mode 1.3.3. Input Clock Mode
1.3.1. USB PHY Timing Characteristics x
1.3.1.1. USB Setup and Hold Relationships 1.3.1.2. USB Controller to PHY Setup and Hold Timing Arcs 1.3.1.3. USB PHY to Controller Setup and Hold Timing Arcs
1.3.1.2. USB Controller to PHY Setup and Hold Timing Arcs x
1.3.1.2.1. USB Controller to PHY Setup Timing Analysis 1.3.1.2.2. USB Controller to PHY Hold Timing Analysis
1.3.1.3. USB PHY to Controller Setup and Hold Timing Arcs x
1.3.1.3.1. USB PHY to Controller Setup Timing Analysis 1.3.1.3.2. USB PHY to Controller Hold Timing Analysis
1.3.3. Input Clock Mode x
1.3.3.1. External Clock Source 1.3.3.2. FPGA Clock Source
1.4. Implementing Input Clock Mode with FPGA Clock Source x
1.4.1. Configuring the HPS USB 2.0 OTG Controller 1.4.2. Select the Controller Clock as Loan I/O 1.4.3. Connecting the Clock in the Top Level Design
1. AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller

1.5. Revision History

Date Version Changes
September 2017 2017.09.22
  • Modified USB PHY Timing Characteristics topic and added subtopics:
    • USB Setup and Hold Relationships
    • USB Controller to PHY Setup and Hold Timing Arcs
    • USB Controller to PHY Setup Timing Analysis
    • USB Controller to PHY Hold Timing Analysis
    • USB PHY to Controller Setup and Hold Timing Arcs
    • USB PHY to Controller Setup Timing Analysis
    • USB PHY to Controller Hold Timing Analysis
July 2014 2014.07.21
  • Corrected the USB MAC Th number value in the USB PHY to USB Controller Hold equation in the USB PHY Timing Characteristics section.
July 2014 2014.07.16
  • Corrected the ClkTrace Td_max value in the USB PHY to USB Controller Setup equation in the USB PHY Timing Characteristics section.
  • Corrected the USB PHY Td_min value in the USB PHY to USB Controller Hold equation in the USB PHY Timing Characteristics section.
July 2014 2014.07.03
  • Modified Table 2: USB MAC Timing Requirements.
  • Added USB PHY Timing Characteristics section.
  • Clarified Output Clock Mode section.
  • Modified Input Clock Mode section.
  • Removed Two Clock Mode, Selecting the PHY Clock, Instantiating a PLL, and Constraining the Design sections.
Level Two Title