AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller

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ID 683601
Date 9/22/2017
Public
Document Table of Contents
Document Table of Contents x
1. AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller
1. AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller x
1.1. ULPI Signals 1.2. HPS USB Controller Timing Characteristics 1.3. PHY Selection 1.4. Implementing Input Clock Mode with FPGA Clock Source 1.5. Revision History
1.2. HPS USB Controller Timing Characteristics x
1.2.1. USB Controller Timing Requirements 1.2.2. USB Controller Setup and Hold Relationships
1.3. PHY Selection x
1.3.1. USB PHY Timing Characteristics 1.3.2. Output Clock Mode 1.3.3. Input Clock Mode
1.3.1. USB PHY Timing Characteristics x
1.3.1.1. USB Setup and Hold Relationships 1.3.1.2. USB Controller to PHY Setup and Hold Timing Arcs 1.3.1.3. USB PHY to Controller Setup and Hold Timing Arcs
1.3.1.2. USB Controller to PHY Setup and Hold Timing Arcs x
1.3.1.2.1. USB Controller to PHY Setup Timing Analysis 1.3.1.2.2. USB Controller to PHY Hold Timing Analysis
1.3.1.3. USB PHY to Controller Setup and Hold Timing Arcs x
1.3.1.3.1. USB PHY to Controller Setup Timing Analysis 1.3.1.3.2. USB PHY to Controller Hold Timing Analysis
1.3.3. Input Clock Mode x
1.3.3.1. External Clock Source 1.3.3.2. FPGA Clock Source
1.4. Implementing Input Clock Mode with FPGA Clock Source x
1.4.1. Configuring the HPS USB 2.0 OTG Controller 1.4.2. Select the Controller Clock as Loan I/O 1.4.3. Connecting the Clock in the Top Level Design
1. AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller

1.4.3. Connecting the Clock in the Top Level Design

The following example shows how to connect the FPGA clock to a Loan I/O when the USB PHY operates in input clock mode using an FPGA clock source from the SoC.

Add the following code snippets to your top-level design file, to connect the clock outputs to the loan I/O: 

// top level module pin defines
// LOANIO10 = mac clock	
inout  wire       LOANIO10, 

// wire instances of the 3 loan IO buses from Platform Designer instance 
wire [66:0] loan_out;
wire [66:0] loan_oe;

// this synthesis keep directive is required in
// order to connect PLL clock outputs to the Loan IO
wire        usb_mac_clk_from_pll    /* synthesis keep */;

// make assignment of the clocks to the appropriate loan IO 
assign loan_out[10]   = usb_mac_clk_from_pll;
assign loan_oe[10]    = 1'b1;

// snippet of Qsys instantiation signal assignments
.hps_0_h2f_loan_io_in                  (),		 // hps_0_h2f_loan_io.in
.hps_0_h2f_loan_io_out                 (loan_out),	//                  .out
.hps_0_h2f_loan_io_oe                  (loan_oe),	 //                  .oe
.hps_io_0_hps_io_gpio_inst_LOANIO10    (LOANIO10),	// hps_io_gpio_inst_LOANIO10
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