Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design Example User Guide

ID 683599
Date 10/05/2020

2.8. Design Example Interface Signals

The Low Latency 40G for ASIC Proto Ethernet testbench is self-contained and does not require you to drive any input signals.

Table 8.   Low Latency 40G for ASIC Proto Ethernet Hardware Design Example Interface Signals
Signal Direction Comments
clk50 Input

Drive at 50 MHz. The intent is to drive it from a 50 MHz oscillator on the board.

The hardware design example routes this clock to the input of an IOPLL on the device and configures the IOPLL to drive a 100 MHz clock internally.

clk_ref Input Drive at 644.53125 MHz.
cpu_resetn Input Resets the IP core. Active low. Drives the global hard reset csr_reset_n to the IP core.
tx_serial[3:0] Output Transceiver PHY output serial data.
rx_serial[3:0] Input Transceiver PHY input serial data.
user_led[7:0] Output Status signals. The hardware design example connects these bits to drive LEDs on the target board. Individual bits reflect the following signal values and clock behavior:
  • [0]: Main reset signal to IP core
  • [1]: Divided version of clk_ref
  • [2]: Divided version of clk50
  • [3]: Divided version of 100 MHz status clock
  • [4]: tx_lanes_stable
  • [5]: rx_block_lock
  • [6]: rx_am_lock
  • [7]: rx_pcs_ready