Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design Example User Guide

ID 683599
Date 10/05/2020
Public

2.5.2. External Loopback Test

Run these steps to perform the external loopback test:
  1. Reset the system.
    sys_reset_digital_analog
  2. Display the clock frequency and PHY status. The rx_clk is set to 312.5 MHz and rx_pcs_ready is set to 1.
    chkphy_status
  3. Start the packet generator.
    start_pkt_gen
  4. Stop the packet generator.
    stop_pkt_gen
  5. Review the number of transmitted and received packets.
    chkmac_stats