Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design Example User Guide

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ID 683599
Date 10/05/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Low Latency 40G for ASIC Proto Ethernet Intel FPGA IP Design Example User Guide Archive 4. Document Revision History for Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Testing the Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Ethernet Toolkit Overview 2.7. Low Latency 40G for ASIC Proto Ethernet Design Example Registers 2.8. Design Example Interface Signals
2.5. Hardware Testing x
2.5.1. Internal Loopback Test 2.5.2. External Loopback Test
2.6. Ethernet Toolkit Overview x
2.6.1. Features
1. Quick Start Guide
2. Design Example Description
3. Low Latency 40G for ASIC Proto Ethernet Intel FPGA IP Design Example User Guide Archive
4. Document Revision History for Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design Example User Guide

4. Document Revision History for Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2020.10.05 20.3 19.1.0
  • Updated procedure in the Generated the Design Example. Added step to select a target development kit.
  • Revised Select USER MAC mode parameter selection. The available options are PCS+MAC and PCS_Only.
  • Added new topic: Ethernet Toolkit Overview.
2020.07.07 20.2 19.1.0 Initial release.

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