Visible to Intel only — GUID: lyp1739906870507
Ixiasoft
2.1.1.1. 200G/400G Ethernet Mode Does Not Support Port-Based Priority Flow Control
2.1.1.2. The F-Tile Ethernet Intel FPGA 200G Hard IP block is de-featured and cannot be used in production devices with OPNs that have no suffix (blank) or 'B' suffix
2.1.1.3. The Deterministic Latency Feature supports on E200 block Six of Eight FGT Channels
2.1.1.4. FHT TX EOJ Spec Compliance Issue
2.1.1.5. Requirement for F-Tile Devices which are Powered and Unconfigured
2.1.1.6. FGT PAM4 Bounding Solution
2.1.1.7. FGT Transceivers Do Not Support Direct EXTEST JTAG Instruction in Boundary Scan Test
2.1.1.8. F-Tile: Unsuccessful TX Equalization
2.1.1.9. Link May Not Downgrade With Corrupt Lanes (F-Tile)
2.1.1.10. Intermittent Equalization Timeout or Speed Degrade during Link Disable, Hot Reset, and Speed Change
2.1.1.11. Link Fault Detection window of the F-Tile Ethernet Intel FPGA Hard IP in 10GE-1 or 25GE-1 mode
2.1.1.12. FHT PMA Transmitter-to-Receiver Internal Serial Loopback operation for error-free BER results
2.1.1.13. F-Tile Ethernet Intel FPGA Hard IP rst_tx_stats and rst_rx_stats register bits might not function correctly
2.1.1.14. F-Tile Ethernet Intel FPGA Hard IP force_rf register bit might not function correctly
2.1.1.15. F-Tile Ethernet Intel FPGA Hard IP tx_pause_request register bit might not function correctly
2.1.1.16. F-Tile Ethernet Intel FPGA Hard IP PTP statistics might not clear correctly
2.1.1.17. F-Tile Ethernet Intel FPGA Hard IP unable to achieve 100% throughput with some variants
2.1.2.1. Gen3/Gen4 link might be established without successfully performing Transmit Equalization (TX EQ)
2.1.2.2. Link may not downgrade with corrupt lanes
2.1.2.3. Malformed TLP incorrectly flagged as ECRC error
2.1.2.4. Assertion of PERST / warm reset during the Functional Level Reset results in PCIe* Link Failure
2.1.2.5. No Support for Page Request Services in Port 2 and Port 3 of 4x4 Configuration
2.1.2.6. Multiple Fatal Error Messages
2.1.2.7. PCIe* x4 cores may report Uncorrectable Fatal Error or Malformed TLP
2.1.2.8. Receiver Errors logged during back-to-back Secondary Bus Resets (SBR) operations when running at Gen 2 speed
2.1.2.9. R-Tile Digital Temperature Sensor Readings
2.1.2.10. R-Tile PCIe* - LCRC Error/Malformed TLP
2.1.2.11. R-Tile PIPE-Direct - rxdatavalid Signal Unexpected Toggling After P1 to P0 Transition
2.1.2.12. Polling.Active time out during Link Disable-Enable loop tests
2.1.2.13. R-Tile PCIe* - Intermittent PCIe* Gen4 EQ time out
2.1.2.14. No response received during read operation on the xcvr_reconfig interface after an FPGA re-configuration
Description
Workaround
Status
2.1.2.15. Slow Completion response from Configuration requests targeting R-Tile Endpoint connected to Downstream port with finite Completion Header/Data credits
2.1.2.16. Bifurcated ports using Independent PERST pins might fail to link up after configuration is complete
2.1.2.17. Port0 might be stuck in Detect when configuring bifurcated ports using Independent PERST pins
2.1.2.18. CXL 1.1 version does not support uncorrectable error reporting when receiving two LLCTRL-Init packet
2.1.3.1. Root Port Legacy Interrupt Status register INTx is stuck HIGH
2.1.3.2. TLP Bypass Error Status register may report receiver errors after the PERST is released
2.1.3.3. Register Implementation while using the SR-IOV Feature
2.1.3.4. Register Implementation while using the Multi-function Feature
2.1.3.5. P-Tile: Unsuccessful TX Equalization
2.1.3.6. Link May Not Degrade With Corrupt Lanes (P-Tile)
2.1.3.7. Warm Reset or PERST Assertion Clears the Sticky Registers
2.1.3.8. Multiple Fatal Error Messages
3.1. 843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When HCR.VM is Set
3.2. 845719: A Load May Read Incorrect Data
3.3. 855871: ETM Does Not Report IDLE State When Disabled Using OSLOCK
3.4. 855872: A Store-Exclusive Instruction Might Pass When it Should Fail
3.5. 711668: Configuration Extension Register Has Wrong Value Status
3.6. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow
3.7. 855873: An Eviction Might Overtake a Cache Clean Operation
3.8. 853172: ETM May Assert AFREADY Before All Data Has Been Output
3.9. 836870: Non-Allocating Reads May Prevent a Store Exclusive From Passing
3.10. 836919: Write of the JMCR in EL0 Does Not Generate an UNDEFINED Exception
3.11. 845819: Instruction Sequences Containing AES Instructions May Produce Incorrect Results
3.12. 851672: ETM May Trace an Incorrect Exception Address
3.13. 851871: ETM May Lose Counter Events While Entering WFx Mode
3.14. 852071: Direct Branch Instructions Executed Before a Trace Flush May be Output in an Atom Packet After Flush Acknowledgment
3.15. 852521: A64 Unconditional Branch May Jump to Incorrect Address
3.16. 855827: PMU Counter Values May Be Inaccurate When Monitoring Certain Events
3.17. 855829: Reads of PMEVCNTR<n> are not Masked by HDCR.HPMN
3.18. 855830: Loads of Mismatched Size May not be Single-Copy Atomic
Visible to Intel only — GUID: lyp1739906870507
Ixiasoft
2.1.2.14. No response received during read operation on the xcvr_reconfig interface after an FPGA re-configuration
Description
The xcvr_reconfig interface in the R-Tile Intel FPGA IP for PCIe requires to have write and read transactions issued in multiples of 8. Not meeting this guideline can cause a lack of response for read operation on the xcvr_reconfig interface after an FPGA re-configuration and it might require a FPGA power cycle in order to recover the access to the xcvr_reconfig interface.
Workaround
The FPGA Application logic must keep track of the number of write and read transactions performed on the xcvr_reconfig interface prior to the FPGA reconfiguration.
The following guideline describes the tracking that needs to be implemented to track the number of transactions prior the FPGA reconfiguration:
- The FPGA Application logic implements two separate transaction counters, one for read operations and one for write operations.
- The FPGA Application logic increases this counter for every transaction issued in the xcvr_reconfig interface.
- Once FPGA Application logic has completed the accesses required on the xcvr_reconfig interface, it must evaluate the counter and confirm it is a multiple of 8.
- In case additional write operations are required, the FPGA Application logic must perform the additional write operations with a value of 0x0 to the address offset 0x6_0000.
- In case additional read transactions are required, the FPGA Application logic must perform the additional read operations to the address offset 0x6_0000. For example, if FPGA Application logic performed only one write operation and two read operations on the xcvr_reconfig interface, as soon as those operations are completed, the FPGA Application logic must perform an additional seven dummy write operations and six dummy read operations to the register offset provided above. This ensures the numbers of transaction issued on the xcvr_reconfig interface is always a multiple of eight.
Status
| Devices Affected | Planned Fix |
|---|---|
|
Quartus® Prime Pro Edition software version 23.3 |