Agilex™ 7 F-Series and I-Series Known Issue List

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ID 683584
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Known Issue List for Agilex™ 7 Devices 3. Arm* Cortex*-A53 MPCore and CoreSight* Errata 4. Agilex™ 7 F-Series and I-Series User Guidelines 5. Document Revision History for the Agilex™ 7 F-Series and I-Series Known Issue List
2. Known Issue List for Agilex™ 7 Devices x
2.1. FPGA 2.2. Hard Processor System
2.1. FPGA x
2.1.1. F-Tile 2.1.2. R-Tile 2.1.3. P-Tile 2.1.4. Configuration and Security
2.1.1. F-Tile x
2.1.1.1. 200G/400G Ethernet Mode Does Not Support Port-Based Priority Flow Control 2.1.1.2. The F-Tile Ethernet 200G Hard IP block is de-featured and cannot be used in production devices with OPNs that have no suffix (blank) or 'B' suffix 2.1.1.3. The Deterministic Latency Feature supports on E200 block Six of Eight FGT Channels 2.1.1.4. FHT TX EOJ Spec Compliance Issue 2.1.1.5. Requirement for F-Tile Devices which are Powered and Unconfigured 2.1.1.6. FGT PAM4 Compliance Support 2.1.1.7. FGT Transceivers Do Not Support Direct EXTEST JTAG Instruction in Boundary Scan Test 2.1.1.8. F-Tile: Unsuccessful TX Equalization 2.1.1.9. Link May Not Downgrade With Corrupt Lanes (F-Tile) 2.1.1.10. Occasional Equalization Timeout or PCIe Link Training Failure to Achieve Expected Link Speed during Link Disable, Hot Reset, and Speed Change 2.1.1.11. Link Fault Detection window of the F-Tile Ethernet Hard IP in 10GE-1 or 25GE-1 mode 2.1.1.12. FHT PMA Transmitter-to-Receiver Internal Serial Loopback operation for error-free BER results 2.1.1.13. F-Tile Ethernet Hard IP rst_tx_stats and rst_rx_stats register bits might not function correctly 2.1.1.14. F-Tile Ethernet Hard IP force_rf register bit might not function correctly 2.1.1.15. F-Tile Ethernet Hard IP tx_pause_request register bit might not function correctly 2.1.1.16. F-Tile Ethernet Hard IP PTP statistics might not clear correctly 2.1.1.17. F-Tile Ethernet Hard IP unable to achieve 100% throughput with some variants 2.1.1.18. F-Tile 400G Ethernet Hard IP RX Priority Flow Control Issue 2.1.1.19. F-Tile Ethernet Hard IP Bidirectional Link Fault Signaling Issue 2.1.1.20. F-Tile SDI II IP and F-Tile PMA/FEC Direct PHY IP with “SDI” configuration rule are not of production quality 2.1.1.21. F-Tile HDMI IP and F-Tile PMA/FEC Direct PHY IP with “HDMI” configuration rule are not of production quality 2.1.1.22. Ethernet Auto-Negotiation and Link Training (AN/LT) designs on F-Tile FGT may not link up when using Quartus Prime Pro Edition software version 25.1.1 and 25.3 2.1.1.23. IEEE 802.3-2022 50GBASE-KR compliance testing instability during Link Training (LT)
2.1.2. R-Tile x
2.1.2.1. Gen3/Gen4 link might be established without successfully performing Transmit Equalization (TX EQ) 2.1.2.2. Link may not downgrade with corrupt lanes 2.1.2.3. Malformed TLP incorrectly flagged as ECRC error 2.1.2.4. Assertion of PERST / warm reset during the Functional Level Reset results in PCIe* Link Failure 2.1.2.5. No Support for Page Request Services in Port 2 and Port 3 of 4x4 Configuration 2.1.2.6. Multiple Fatal Error Messages 2.1.2.7. PCIe* x4 cores may report Uncorrectable Fatal Error or Malformed TLP 2.1.2.8. Receiver Errors logged during back-to-back Secondary Bus Resets (SBR) operations when running at Gen 2 speed 2.1.2.9. R-Tile Digital Temperature Sensor Readings 2.1.2.10. R-Tile PCIe* - LCRC Error/Malformed TLP 2.1.2.11. R-Tile PIPE-Direct - rxdatavalid Signal Unexpected Toggling After P1 to P0 Transition 2.1.2.12. Polling.Active time out during Link Disable-Enable loop tests 2.1.2.13. R-Tile PCIe* - Intermittent PCIe* Gen4 EQ time out 2.1.2.14. No response received during read operation on the xcvr_reconfig interface after an FPGA re-configuration 2.1.2.15. Slow Completion response from Configuration requests targeting R-Tile Endpoint connected to Downstream port with finite Completion Header/Data credits 2.1.2.16. Bifurcated ports using Independent PERST pins might fail to link up after configuration is complete Description Impacted Modes Workaround Status 2.1.2.17. Port0 might be stuck in Detect when configuring bifurcated ports using Independent PERST pins 2.1.2.18. CXL 1.1 version does not support uncorrectable error reporting when receiving two LLCTRL-Init packet 2.1.2.19. R-tile might report Fatal Error in the Advance Error Reporting (AER) registers when using Address Translation Service (ATS)
2.1.3. P-Tile x
2.1.3.1. Root Port Legacy Interrupt Status register INTx is stuck HIGH 2.1.3.2. TLP Bypass Error Status register may report receiver errors after the PERST is released 2.1.3.3. Register Implementation while using the SR-IOV Feature 2.1.3.4. Register Implementation while using the Multi-function Feature 2.1.3.5. P-Tile: Unsuccessful TX Equalization 2.1.3.6. Link May Not Degrade With Corrupt Lanes (P-Tile) 2.1.3.7. Warm Reset or PERST Assertion Clears the Sticky Registers 2.1.3.8. Multiple Fatal Error Messages
2.1.4. Configuration and Security x
2.1.4.1. FPGA Reconfiguration May Cause Device to Halt 2.1.4.2. Secure Device Manager May Disable Physically Unclonable Function 2.1.4.3. Reset Timing Violation for QSPI Flash Specification
2.2. Hard Processor System x
2.2.1. Write Data Can Appear at an AXI Interface before the Write Address, which can Cause a Deadlock Condition 2.2.2. HPS EMAC Rx interface stuck in unresponsive state
3. Arm* Cortex*-A53 MPCore and CoreSight* Errata x
3.1. 843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When HCR.VM is Set 3.2. 845719: A Load May Read Incorrect Data 3.3. 855871: ETM Does Not Report IDLE State When Disabled Using OSLOCK 3.4. 855872: A Store-Exclusive Instruction Might Pass When it Should Fail 3.5. 711668: Configuration Extension Register Has Wrong Value Status 3.6. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 3.7. 855873: An Eviction Might Overtake a Cache Clean Operation 3.8. 853172: ETM May Assert AFREADY Before All Data Has Been Output 3.9. 836870: Non-Allocating Reads May Prevent a Store Exclusive From Passing 3.10. 836919: Write of the JMCR in EL0 Does Not Generate an UNDEFINED Exception 3.11. 845819: Instruction Sequences Containing AES Instructions May Produce Incorrect Results 3.12. 851672: ETM May Trace an Incorrect Exception Address 3.13. 851871: ETM May Lose Counter Events While Entering WFx Mode 3.14. 852071: Direct Branch Instructions Executed Before a Trace Flush May be Output in an Atom Packet After Flush Acknowledgment 3.15. 852521: A64 Unconditional Branch May Jump to Incorrect Address 3.16. 855827: PMU Counter Values May Be Inaccurate When Monitoring Certain Events 3.17. 855829: Reads of PMEVCNTR<n> are not Masked by HDCR.HPMN 3.18. 855830: Loads of Mismatched Size May not be Single-Copy Atomic
1. About this Document
2. Known Issue List for Agilex™ 7 Devices
3. Arm* Cortex*-A53 MPCore and CoreSight* Errata
4. Agilex™ 7 F-Series and I-Series User Guidelines
5. Document Revision History for the Agilex™ 7 F-Series and I-Series Known Issue List

2.1.2.16. Bifurcated ports using Independent PERST pins might fail to link up after configuration is complete

Description

When using Enable Independent PERST pins to implement bifurcated x8x8 ports in R-Tile Avalon Streaming IP for PCI Express in Endpoint mode, both ports might fail to link up under the following scenarios:
  • Scenario 1: When FPGA is configured with

    -refclk0 unavailable, i_pin_perst0_n deasserted (1’b1) and

    -refclk1 stable and free running, i_pin_perst1_n deasserted (1’b1) and

    -refclk2 stable and free running, i_pin_perst_n deasserted (1’b1),

    then Port 0 is expected to be in reset, while Port 1 fails to link up. Toggling the i_pin_perst1_n or i_pin_perst_n does not recover the link on Port 1. This issue is fixed in Quartus® Prime Pro Edition software version 24.3 (Port 0 in reset, Port 1 links up). To allow Port 0 to link up once the refclk0 becomes available after FPGA configuration is complete, you must toggle i_pin_perst0_n. Toggling the i_pin_perst_n causes both the links to fail link up and the FPGA must be reconfigured to recover from this state.
  • Scenario 2: When FPGA is configured with

    -refclk0 stable and free running, i_pin_perst0_n deasserted (1’b1) and

    -refclk1 unavailable, i_pin_perst1_n deasserted (1’b1) and

    -refclk2 stable and free running, i_pin_perst_n deasserted (1’b1),

    then Port 0 fails to link up, while Port 1 is expected to be in reset. Toggling the i_pin_perst0_n or i_pin_perst_n does not recover the link on Port 0. This issue is fixed in Quartus® Prime Pro Edition software version 24.3 (Port 0 links up, Port 1 in reset). To allow Port 1 to link up once the refclk1 becomes available after FPGA configuration is complete, you must toggle i_pin_perst1_n. Toggling the i_pin_perst_n causes both the links to fail link up and the FPGA must be reconfigured to recover from this state.

Impacted Modes

  • PCIe* IP in endpoint mode

Workaround

None.

Status

Table 42.  Device Status Table
Devices Affected Planned Fix
  • AGIx041R29xxxxxx
  • AGIx041R31Exxxxx
 Quartus® Prime Pro Edition software version 24.3
Level Two Title