Intel Agilex® 7 F-Series and I-Series Known Issue List

ID 683584
Date 5/03/2023
Document Table of Contents

3.10. 836919: Write of the JMCR in EL0 Does Not Generate an UNDEFINED Exception


When EL0 is using AArch32 register width and a write is performed in EL0 to the Arm* Jazelle® Main Configuration Register (JMCR), the write should be UNDEFINED. Because of this erratum, the write is permitted but ignored.

The erratum occurs under the following conditions:
  • The processor is executing in AArch32 user mode.
  • A write to the JMCR is executed, using the instruction MCR p14,7,<Rt>,c2,c0,0.


Rather than treating the MCR instruction as UNDEFINED, a write to the JMCR is ignored.


No available workaround.


Category 3