Agilex™ 7 F-Series and I-Series Known Issue List

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ID 683584
Date 9/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Known Issue List for Agilex™ 7 Devices 3. Arm* Cortex*-A53 MPCore and CoreSight* Errata 4. Agilex™ 7 F-Series and I-Series User Guidelines 5. Document Revision History for the Agilex™ 7 F-Series and I-Series Known Issue List
2. Known Issue List for Agilex™ 7 Devices x
2.1. FPGA 2.2. Hard Processor System
2.1. FPGA x
2.1.1. F-Tile 2.1.2. R-Tile 2.1.3. P-Tile 2.1.4. Configuration and Security
2.1.1. F-Tile x
2.1.1.1. 200G/400G Ethernet Mode Does Not Support Port-Based Priority Flow Control 2.1.1.2. The F-Tile Ethernet Intel FPGA 200G Hard IP block is de-featured and cannot be used in production devices with OPNs that have no suffix (blank) or 'B' suffix 2.1.1.3. The Deterministic Latency Feature supports on E200 block Six of Eight FGT Channels 2.1.1.4. FHT TX EOJ Spec Compliance Issue 2.1.1.5. Requirement for F-Tile Devices which are Powered and Unconfigured 2.1.1.6. FGT PAM4 Compliance Support 2.1.1.7. FGT Transceivers Do Not Support Direct EXTEST JTAG Instruction in Boundary Scan Test 2.1.1.8. F-Tile: Unsuccessful TX Equalization 2.1.1.9. Link May Not Downgrade With Corrupt Lanes (F-Tile) 2.1.1.10. Occasional Equalization Timeout or PCIe Link Training Failure to Achieve Expected Link Speed during Link Disable, Hot Reset, and Speed Change 2.1.1.11. Link Fault Detection window of the F-Tile Ethernet Intel FPGA Hard IP in 10GE-1 or 25GE-1 mode 2.1.1.12. FHT PMA Transmitter-to-Receiver Internal Serial Loopback operation for error-free BER results 2.1.1.13. F-Tile Ethernet Intel FPGA Hard IP rst_tx_stats and rst_rx_stats register bits might not function correctly 2.1.1.14. F-Tile Ethernet Intel FPGA Hard IP force_rf register bit might not function correctly 2.1.1.15. F-Tile Ethernet Intel FPGA Hard IP tx_pause_request register bit might not function correctly 2.1.1.16. F-Tile Ethernet Intel FPGA Hard IP PTP statistics might not clear correctly 2.1.1.17. F-Tile Ethernet Intel FPGA Hard IP unable to achieve 100% throughput with some variants 2.1.1.18. F-Tile 400G Ethernet Intel FPGA Hard IP RX Priority Flow Control Issue Description Workaround Status 2.1.1.19. F-Tile Ethernet Intel FPGA Hard IP Bidirectional Link Fault Signaling Issue 2.1.1.20. F-Tile SDI II Intel FPGA IP and F-Tile PMA/FEC Direct PHY Intel FPGA IP with “SDI” configuration rule are not of production quality 2.1.1.21. F-Tile HDMI Intel FPGA IP and F-Tile PMA/FEC Direct PHY Intel FPGA IP with “HDMI” configuration rule are not of production quality
2.1.2. R-Tile x
2.1.2.1. Gen3/Gen4 link might be established without successfully performing Transmit Equalization (TX EQ) 2.1.2.2. Link may not downgrade with corrupt lanes 2.1.2.3. Malformed TLP incorrectly flagged as ECRC error 2.1.2.4. Assertion of PERST / warm reset during the Functional Level Reset results in PCIe* Link Failure 2.1.2.5. No Support for Page Request Services in Port 2 and Port 3 of 4x4 Configuration 2.1.2.6. Multiple Fatal Error Messages 2.1.2.7. PCIe* x4 cores may report Uncorrectable Fatal Error or Malformed TLP 2.1.2.8. Receiver Errors logged during back-to-back Secondary Bus Resets (SBR) operations when running at Gen 2 speed 2.1.2.9. R-Tile Digital Temperature Sensor Readings 2.1.2.10. R-Tile PCIe* - LCRC Error/Malformed TLP 2.1.2.11. R-Tile PIPE-Direct - rxdatavalid Signal Unexpected Toggling After P1 to P0 Transition 2.1.2.12. Polling.Active time out during Link Disable-Enable loop tests 2.1.2.13. R-Tile PCIe* - Intermittent PCIe* Gen4 EQ time out 2.1.2.14. No response received during read operation on the xcvr_reconfig interface after an FPGA re-configuration 2.1.2.15. Slow Completion response from Configuration requests targeting R-Tile Endpoint connected to Downstream port with finite Completion Header/Data credits 2.1.2.16. Bifurcated ports using Independent PERST pins might fail to link up after configuration is complete 2.1.2.17. Port0 might be stuck in Detect when configuring bifurcated ports using Independent PERST pins 2.1.2.18. CXL 1.1 version does not support uncorrectable error reporting when receiving two LLCTRL-Init packet 2.1.2.19. R-tile might report Fatal Error in the Advance Error Reporting (AER) registers when using Address Translation Service (ATS)
2.1.3. P-Tile x
2.1.3.1. Root Port Legacy Interrupt Status register INTx is stuck HIGH 2.1.3.2. TLP Bypass Error Status register may report receiver errors after the PERST is released 2.1.3.3. Register Implementation while using the SR-IOV Feature 2.1.3.4. Register Implementation while using the Multi-function Feature 2.1.3.5. P-Tile: Unsuccessful TX Equalization 2.1.3.6. Link May Not Degrade With Corrupt Lanes (P-Tile) 2.1.3.7. Warm Reset or PERST Assertion Clears the Sticky Registers 2.1.3.8. Multiple Fatal Error Messages
2.1.4. Configuration and Security x
2.1.4.1. FPGA Reconfiguration May Cause Device to Halt 2.1.4.2. Secure Device Manager May Disable Physically Unclonable Function 2.1.4.3. Reset Timing Violation for QSPI Flash Specification
2.2. Hard Processor System x
2.2.1. Write Data Can Appear at an AXI Interface before the Write Address, which can Cause a Deadlock Condition 2.2.2. HPS EMAC Rx interface stuck in unresponsive state
3. Arm* Cortex*-A53 MPCore and CoreSight* Errata x
3.1. 843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When HCR.VM is Set 3.2. 845719: A Load May Read Incorrect Data 3.3. 855871: ETM Does Not Report IDLE State When Disabled Using OSLOCK 3.4. 855872: A Store-Exclusive Instruction Might Pass When it Should Fail 3.5. 711668: Configuration Extension Register Has Wrong Value Status 3.6. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 3.7. 855873: An Eviction Might Overtake a Cache Clean Operation 3.8. 853172: ETM May Assert AFREADY Before All Data Has Been Output 3.9. 836870: Non-Allocating Reads May Prevent a Store Exclusive From Passing 3.10. 836919: Write of the JMCR in EL0 Does Not Generate an UNDEFINED Exception 3.11. 845819: Instruction Sequences Containing AES Instructions May Produce Incorrect Results 3.12. 851672: ETM May Trace an Incorrect Exception Address 3.13. 851871: ETM May Lose Counter Events While Entering WFx Mode 3.14. 852071: Direct Branch Instructions Executed Before a Trace Flush May be Output in an Atom Packet After Flush Acknowledgment 3.15. 852521: A64 Unconditional Branch May Jump to Incorrect Address 3.16. 855827: PMU Counter Values May Be Inaccurate When Monitoring Certain Events 3.17. 855829: Reads of PMEVCNTR<n> are not Masked by HDCR.HPMN 3.18. 855830: Loads of Mismatched Size May not be Single-Copy Atomic
1. About this Document
2. Known Issue List for Agilex™ 7 Devices
3. Arm* Cortex*-A53 MPCore and CoreSight* Errata
4. Agilex™ 7 F-Series and I-Series User Guidelines
5. Document Revision History for the Agilex™ 7 F-Series and I-Series Known Issue List

2.1.1.18. F-Tile 400G Ethernet Intel FPGA Hard IP RX Priority Flow Control Issue

Description

When using the F-Tile 400G Ethernet Intel FPGA Hard IP with Priority Flow Control (PFC) enabled, the RX MAC might incorrectly turn a priority queue from the XOFF state to the XON state when all of the following conditions are met:

  • The RX MAC receives 2 back-to-back PFC frames with no other type of Ethernet frame between them
  • The second PFC frame is sent before the quanta of the first PFC frame expires
  • The Priority Enable Vector (PEV) of the second PFC frame has some of the same classes enabled as the first PFC frame
  • The packet arrangement on the RX MAC MII interface is such that the second PFC frame’s PEV and End-of-Packet appear in the same MII clock cycle

Workaround

None.

Status

Table 21.  Device Status Table
Devices Affected Planned Fix
  • AGFxxxxxxxxxxxx
  • AGIxxxxxxxxxxxx
 This issue is planned to be fixed in a future release of the Quartus® Prime Pro Edition software
Level Two Title