E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 4/10/2023

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Document Table of Contents

3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide

The E-tile CPRI PHY Intel® FPGA IP core for Intel® Stratix® 10 devices provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

In addition, you can download the compiled hardware design to the Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit. Intel® provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

The E-tile CPRI PHY Intel® FPGA IP core provides the capability of generating design examples for all supported combinations of number of CPRI channels and CPRI line bit rates. The testbench and design example support numerous parameter combinations of the E-tile CPRI PHY Intel® FPGA IP core.

Figure 26. Development Steps for the Design Example