E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 4/10/2023
Public

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2.1.6.3. 100GE PCS Only with Optional (528,514) RS-FEC or (544,514) RS-FEC, and Optional PTP Hardware Design Example

To turn on the System Console and test the hardware design example, follow these steps:

  1. After the hardware design example is configured on the Intel® Stratix® 10 device, in the Intel® Quartus® Prime Pro Edition software, on the Tools menu, click System Debugging Tools > System Console.
  2. In the Tcl Console pane, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest.
  3. Type source main.tcl to open a connection to the JTAG master.
  4. Type set_jtag <Master Number> command to select the appropriate JTAG master. (For example: set_jtag 1)
  5. Type pcs_only_traffic_test <number of iteration> to run the specified iteration of PCS only with (528,514) RS-FEC hardware design example test. If no value is specified, the test runs only 1 iteration. Each packet generated for every iterations are in random number of frames, size, and types.
  6. Type pcs_only_traffic_test_pam4 <number of interation> to run the specified iteration of PCS only with (544,514) RS-FEC hardware design example test. If no value is specified, the test runs only 1 iteration. Each packet generated for every iterations are in random number of frames, size, and types.