E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 4/10/2023

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3.2.5. Design Example Register Map for Reconfiguration

Table 21.   E-tile CPRI PHY Intel® FPGA IP Hardware Design Example PHY Register Map
Channel Number Word Offset Register Type
0 0x000000 CPRI registers
0x010000 RS-FEC configuration registers
0x100000 Transceiver registers
1 0x200000 CPRI registers
0x300000 Transceiver registers
2 0x400000 CPRI registers
0x500000 Transceiver registers
3 0x600000 CPRI registers
0x700000 Transceiver registers